address comment

Author: diggerlin

llvm/test/CodeGen/PowerPC/mtvsrbmi.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; Verify whether the generated assembly for the following function includes the mtvsrbmi instruction.
 ; vector unsigned char v00FF()
 ; {
@@ -8,7 +9,12 @@
 ; RUN: llc < %s -ppc-asm-full-reg-names  -mtriple=powerpc-ibm-aix -mcpu=pwr10  -verify-machineinstrs \
 ; RUN:   | FileCheck %s --check-prefix=CHECK
 
-define dso_local noundef range(i8 -1, 1) <16 x i8> @_Z5v00FFv() local_unnamed_addr {
+define dso_local noundef range(i8 -1, 1) <16 x i8> @_Z5v00FFv() {
+; CHECK-LABEL: _Z5v00FFv:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz r3, L..C0(r2) # %const.0
+; CHECK-NEXT:    lxv vs34, 0(r3)
+; CHECK-NEXT:    blr
 entry:
   ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
 }
@@ -33,6 +39,6 @@ entry:
 
 ; CHECK:      ._Z5v00FFv:
 ; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT:   lwz r3, L..C0(r2) 
+; CHECK-NEXT:   lwz r3, L..C0(r2)
 ; CHECK-NEXT:   lxv vs34, 0(r3)
-; CHECK-NEXT:   blr 
+; CHECK-NEXT:   blr