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alexey-bataevalexey-bataev
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[𝘀𝗽𝗿] initial version
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 52 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -5103,7 +5103,6 @@ static SDValue lowerShuffleViaVRegSplitting(ShuffleVectorSDNode *SVN,
51035103
SDValue V1 = SVN->getOperand(0);
51045104
SDValue V2 = SVN->getOperand(1);
51055105
ArrayRef<int> Mask = SVN->getMask();
5106-
unsigned NumElts = VT.getVectorNumElements();
51075106

51085107
// If we don't know exact data layout, not much we can do. If this
51095108
// is already m1 or smaller, no point in splitting further.
@@ -5120,58 +5119,70 @@ static SDValue lowerShuffleViaVRegSplitting(ShuffleVectorSDNode *SVN,
51205119

51215120
MVT ElemVT = VT.getVectorElementType();
51225121
unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits();
5123-
unsigned VRegsPerSrc = NumElts / ElemsPerVReg;
5124-
5125-
SmallVector<std::pair<int, SmallVector<int>>>
5126-
OutMasks(VRegsPerSrc, {-1, {}});
5127-
5128-
// Check if our mask can be done as a 1-to-1 mapping from source
5129-
// to destination registers in the group without needing to
5130-
// write each destination more than once.
5131-
for (unsigned DstIdx = 0; DstIdx < Mask.size(); DstIdx++) {
5132-
int DstVecIdx = DstIdx / ElemsPerVReg;
5133-
int DstSubIdx = DstIdx % ElemsPerVReg;
5134-
int SrcIdx = Mask[DstIdx];
5135-
if (SrcIdx < 0 || (unsigned)SrcIdx >= 2 * NumElts)
5136-
continue;
5137-
int SrcVecIdx = SrcIdx / ElemsPerVReg;
5138-
int SrcSubIdx = SrcIdx % ElemsPerVReg;
5139-
if (OutMasks[DstVecIdx].first == -1)
5140-
OutMasks[DstVecIdx].first = SrcVecIdx;
5141-
if (OutMasks[DstVecIdx].first != SrcVecIdx)
5142-
// Note: This case could easily be handled by keeping track of a chain
5143-
// of source values and generating two element shuffles below. This is
5144-
// less an implementation question, and more a profitability one.
5145-
return SDValue();
5146-
5147-
OutMasks[DstVecIdx].second.resize(ElemsPerVReg, -1);
5148-
OutMasks[DstVecIdx].second[DstSubIdx] = SrcSubIdx;
5149-
}
51505122

51515123
EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
51525124
MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg);
51535125
MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget);
51545126
assert(M1VT == getLMUL1VT(M1VT));
51555127
unsigned NumOpElts = M1VT.getVectorMinNumElements();
5156-
SDValue Vec = DAG.getUNDEF(ContainerVT);
5128+
unsigned NormalizedVF = ContainerVT.getVectorMinNumElements();
5129+
unsigned NumOfSrcRegs = NormalizedVF / NumOpElts;
5130+
unsigned NumOfDestRegs = NormalizedVF / NumOpElts;
51575131
// The following semantically builds up a fixed length concat_vector
51585132
// of the component shuffle_vectors. We eagerly lower to scalable here
51595133
// to avoid DAG combining it back to a large shuffle_vector again.
51605134
V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
51615135
V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget);
5162-
for (unsigned DstVecIdx = 0 ; DstVecIdx < OutMasks.size(); DstVecIdx++) {
5163-
auto &[SrcVecIdx, SrcSubMask] = OutMasks[DstVecIdx];
5164-
if (SrcVecIdx == -1)
5136+
SmallVector<SDValue> SubRegs(NumOfDestRegs);
5137+
unsigned RegCnt = 0;
5138+
unsigned PrevCnt = 0;
5139+
processShuffleMasks(
5140+
Mask, NumOfSrcRegs, NumOfDestRegs, NumOfDestRegs,
5141+
[&]() {
5142+
PrevCnt = RegCnt;
5143+
++RegCnt;
5144+
},
5145+
[&, &DAG = DAG](ArrayRef<int> SrcSubMask, unsigned SrcVecIdx,
5146+
unsigned DstVecIdx) {
5147+
SDValue SrcVec = SrcVecIdx >= NumOfSrcRegs ? V2 : V1;
5148+
unsigned ExtractIdx = (SrcVecIdx % NumOfSrcRegs) * NumOpElts;
5149+
SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec,
5150+
DAG.getVectorIdxConstant(ExtractIdx, DL));
5151+
SubVec = convertFromScalableVector(OneRegVT, SubVec, DAG, Subtarget);
5152+
SubVec = DAG.getVectorShuffle(OneRegVT, DL, SubVec, SubVec, SrcSubMask);
5153+
SubRegs[RegCnt] = convertToScalableVector(M1VT, SubVec, DAG, Subtarget);
5154+
PrevCnt = RegCnt;
5155+
++RegCnt;
5156+
},
5157+
[&, &DAG = DAG](ArrayRef<int> SrcSubMask, unsigned Idx1, unsigned Idx2) {
5158+
if (PrevCnt + 1 == RegCnt)
5159+
++RegCnt;
5160+
SDValue SubVec1 = SubRegs[PrevCnt + 1];
5161+
if (!SubVec1) {
5162+
SDValue SrcVec = Idx1 >= NumOfSrcRegs ? V2 : V1;
5163+
unsigned ExtractIdx = (Idx1 % NumOfSrcRegs) * NumOpElts;
5164+
SubVec1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec,
5165+
DAG.getVectorIdxConstant(ExtractIdx, DL));
5166+
}
5167+
SubVec1 = convertFromScalableVector(OneRegVT, SubVec1, DAG, Subtarget);
5168+
SDValue SrcVec = Idx2 >= NumOfSrcRegs ? V2 : V1;
5169+
unsigned ExtractIdx = (Idx2 % NumOfSrcRegs) * NumOpElts;
5170+
SDValue SubVec2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec,
5171+
DAG.getVectorIdxConstant(ExtractIdx, DL));
5172+
SubVec2 = convertFromScalableVector(OneRegVT, SubVec2, DAG, Subtarget);
5173+
SubVec1 =
5174+
DAG.getVectorShuffle(OneRegVT, DL, SubVec1, SubVec2, SrcSubMask);
5175+
SubVec1 = convertToScalableVector(M1VT, SubVec1, DAG, Subtarget);
5176+
SubRegs[PrevCnt + 1] = SubVec1;
5177+
});
5178+
assert(RegCnt == NumOfDestRegs && "Whole vector must be processed");
5179+
SDValue Vec = DAG.getUNDEF(ContainerVT);
5180+
for (auto [I, V] : enumerate(SubRegs)) {
5181+
if (!V)
51655182
continue;
5166-
unsigned ExtractIdx = (SrcVecIdx % VRegsPerSrc) * NumOpElts;
5167-
SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1;
5168-
SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec,
5169-
DAG.getVectorIdxConstant(ExtractIdx, DL));
5170-
SubVec = convertFromScalableVector(OneRegVT, SubVec, DAG, Subtarget);
5171-
SubVec = DAG.getVectorShuffle(OneRegVT, DL, SubVec, SubVec, SrcSubMask);
5172-
SubVec = convertToScalableVector(M1VT, SubVec, DAG, Subtarget);
5173-
unsigned InsertIdx = DstVecIdx * NumOpElts;
5174-
Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, Vec, SubVec,
5183+
unsigned InsertIdx = I * NumOpElts;
5184+
5185+
Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, Vec, V,
51755186
DAG.getVectorIdxConstant(InsertIdx, DL));
51765187
}
51775188
return convertFromScalableVector(VT, Vec, DAG, Subtarget);

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll‎

Lines changed: 41 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -168,12 +168,11 @@ define <4 x i64> @m2_splat_into_slide_two_source_v2_lo(<4 x i64> %v1, <4 x i64>
168168
define <4 x i64> @m2_splat_into_slide_two_source(<4 x i64> %v1, <4 x i64> %v2) vscale_range(2,2) {
169169
; CHECK-LABEL: m2_splat_into_slide_two_source:
170170
; CHECK: # %bb.0:
171-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
172-
; CHECK-NEXT: vmv.v.i v0, 12
173-
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
171+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
172+
; CHECK-NEXT: vslidedown.vi v13, v10, 1
173+
; CHECK-NEXT: vslideup.vi v13, v11, 1
174174
; CHECK-NEXT: vrgather.vi v12, v8, 0
175-
; CHECK-NEXT: vslideup.vi v12, v10, 1, v0.t
176-
; CHECK-NEXT: vmv.v.v v8, v12
175+
; CHECK-NEXT: vmv2r.v v8, v12
177176
; CHECK-NEXT: ret
178177
%res = shufflevector <4 x i64> %v1, <4 x i64> %v2, <4 x i32> <i32 0, i32 0, i32 5, i32 6>
179178
ret <4 x i64> %res
@@ -183,18 +182,17 @@ define void @shuffle1(ptr %explicit_0, ptr %explicit_1) vscale_range(2,2) {
183182
; CHECK-LABEL: shuffle1:
184183
; CHECK: # %bb.0:
185184
; CHECK-NEXT: addi a0, a0, 252
185+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
186+
; CHECK-NEXT: vmv.v.i v8, 0
186187
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
187-
; CHECK-NEXT: vid.v v8
188+
; CHECK-NEXT: vid.v v10
188189
; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
189-
; CHECK-NEXT: vle32.v v9, (a0)
190-
; CHECK-NEXT: li a0, 175
191-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
192-
; CHECK-NEXT: vsrl.vi v8, v8, 1
193-
; CHECK-NEXT: vmv.s.x v0, a0
194-
; CHECK-NEXT: vadd.vi v8, v8, 1
195-
; CHECK-NEXT: vrgather.vv v11, v9, v8
196-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
197-
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
190+
; CHECK-NEXT: vle32.v v11, (a0)
191+
; CHECK-NEXT: vmv.v.i v0, 5
192+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
193+
; CHECK-NEXT: vsrl.vi v10, v10, 1
194+
; CHECK-NEXT: vadd.vi v10, v10, 1
195+
; CHECK-NEXT: vrgather.vv v9, v11, v10, v0.t
198196
; CHECK-NEXT: addi a0, a1, 672
199197
; CHECK-NEXT: vs2r.v v8, (a0)
200198
; CHECK-NEXT: ret
@@ -211,15 +209,15 @@ define void @shuffle1(ptr %explicit_0, ptr %explicit_1) vscale_range(2,2) {
211209
define <16 x float> @shuffle2(<4 x float> %a) vscale_range(2,2) {
212210
; CHECK-LABEL: shuffle2:
213211
; CHECK: # %bb.0:
214-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
215-
; CHECK-NEXT: vid.v v9
216-
; CHECK-NEXT: li a0, -97
217-
; CHECK-NEXT: vadd.vv v9, v9, v9
218-
; CHECK-NEXT: vrsub.vi v9, v9, 4
219-
; CHECK-NEXT: vmv.s.x v0, a0
220-
; CHECK-NEXT: vrgather.vv v13, v8, v9
221212
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
222-
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
213+
; CHECK-NEXT: vmv1r.v v12, v8
214+
; CHECK-NEXT: vmv.v.i v8, 0
215+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
216+
; CHECK-NEXT: vid.v v13
217+
; CHECK-NEXT: vadd.vv v13, v13, v13
218+
; CHECK-NEXT: vmv.v.i v0, 6
219+
; CHECK-NEXT: vrsub.vi v13, v13, 4
220+
; CHECK-NEXT: vrgather.vv v9, v12, v13, v0.t
223221
; CHECK-NEXT: ret
224222
%b = extractelement <4 x float> %a, i32 2
225223
%c = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %b, i32 5
@@ -231,16 +229,15 @@ define <16 x float> @shuffle2(<4 x float> %a) vscale_range(2,2) {
231229
define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vscale_range(2,2) {
232230
; RV32-LABEL: extract_any_extend_vector_inreg_v16i64:
233231
; RV32: # %bb.0:
234-
; RV32-NEXT: li a1, 16
235-
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
232+
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
236233
; RV32-NEXT: vmv.v.i v16, 0
237-
; RV32-NEXT: vmv.s.x v0, a1
234+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
235+
; RV32-NEXT: vmv.v.i v0, 1
238236
; RV32-NEXT: li a1, 32
239-
; RV32-NEXT: vrgather.vi v16, v8, 15, v0.t
240-
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
237+
; RV32-NEXT: vrgather.vi v18, v15, 1, v0.t
238+
; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma
241239
; RV32-NEXT: vslidedown.vx v8, v16, a0
242240
; RV32-NEXT: vmv.x.s a0, v8
243-
; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma
244241
; RV32-NEXT: vsrl.vx v8, v8, a1
245242
; RV32-NEXT: vmv.x.s a1, v8
246243
; RV32-NEXT: ret
@@ -258,13 +255,14 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vsca
258255
; RV64-NEXT: addi s0, sp, 256
259256
; RV64-NEXT: .cfi_def_cfa s0, 0
260257
; RV64-NEXT: andi sp, sp, -128
261-
; RV64-NEXT: li a1, -17
258+
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
259+
; RV64-NEXT: vmv.v.i v0, 1
262260
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
263-
; RV64-NEXT: vmv.s.x v0, a1
264-
; RV64-NEXT: vrgather.vi v16, v8, 15
265-
; RV64-NEXT: vmerge.vim v8, v16, 0, v0
261+
; RV64-NEXT: vmv.v.i v16, 0
262+
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
263+
; RV64-NEXT: vrgather.vi v18, v15, 1, v0.t
266264
; RV64-NEXT: mv s2, sp
267-
; RV64-NEXT: vs8r.v v8, (s2)
265+
; RV64-NEXT: vs8r.v v16, (s2)
268266
; RV64-NEXT: andi a0, a0, 15
269267
; RV64-NEXT: li a1, 8
270268
; RV64-NEXT: call __muldi3
@@ -290,21 +288,16 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vsca
290288
define <4 x double> @shuffles_add(<4 x double> %0, <4 x double> %1) vscale_range(2,2) {
291289
; CHECK-LABEL: shuffles_add:
292290
; CHECK: # %bb.0:
291+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
292+
; CHECK-NEXT: vmv1r.v v13, v10
293+
; CHECK-NEXT: vslideup.vi v13, v11, 1
294+
; CHECK-NEXT: vmv1r.v v8, v9
295+
; CHECK-NEXT: vmv.v.i v0, 1
296+
; CHECK-NEXT: vrgather.vi v12, v9, 0
297+
; CHECK-NEXT: vmv1r.v v9, v11
298+
; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
293299
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
294-
; CHECK-NEXT: vrgather.vi v12, v8, 2
295-
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
296-
; CHECK-NEXT: vid.v v14
297-
; CHECK-NEXT: vmv.v.i v0, 12
298-
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
299-
; CHECK-NEXT: vrgather.vi v16, v8, 3
300-
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
301-
; CHECK-NEXT: vadd.vv v8, v14, v14
302-
; CHECK-NEXT: vadd.vi v9, v8, -4
303-
; CHECK-NEXT: vadd.vi v8, v8, -3
304-
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
305-
; CHECK-NEXT: vrgatherei16.vv v12, v10, v9, v0.t
306-
; CHECK-NEXT: vrgatherei16.vv v16, v10, v8, v0.t
307-
; CHECK-NEXT: vfadd.vv v8, v12, v16
300+
; CHECK-NEXT: vfadd.vv v8, v12, v8
308301
; CHECK-NEXT: ret
309302
%3 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
310303
%4 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>

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