@@ -278,6 +278,21 @@ let Predicates = [HasVSX, IsISAFuture] in {
278
278
//---------------------------- Anonymous Patterns ----------------------------//
279
279
// Predicate combinations available:
280
280
281
+ // Load/Store VSX Vector with Right Length (Left-justified).
282
+ def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
283
+ def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
284
+ def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
285
+ $RB)>;
286
+ def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
287
+ $RB)>;
288
+
289
+ // Load/Store VSX Vector pair with Right Length (Left-justified).
290
+ def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
291
+ def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
292
+ def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
293
+ $RA, $RB)>;
294
+ def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
295
+ $RA, $RB)>;
281
296
282
297
//---------------------------- Instruction aliases ---------------------------//
283
298
// Predicate combinations available:
@@ -307,21 +322,3 @@ let Predicates = [HasVSX, IsISAFuture] in {
307
322
def : InstAlias<"xxgfmul128xts $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,
308
323
vsrc:$XB, 1)>;
309
324
}
310
-
311
- //---------------------------- Anonymous Patterns ----------------------------//
312
-
313
- // Load/Store VSX Vector with Right Length (Left-justified).
314
- def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
315
- def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
316
- def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
317
- $RB)>;
318
- def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
319
- $RB)>;
320
-
321
- // Load/Store VSX Vector pair with Right Length (Left-justified).
322
- def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
323
- def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
324
- def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
325
- $RA, $RB)>;
326
- def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
327
- $RA, $RB)>;
0 commit comments