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[TableGen] Remove the name from the union in OpData in PseudoLoweringEmitter and CompressInstEmitter (#147896)
We can use an anonymous union here, the name doesn't provide any additional information.
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2 files changed

+30
-34
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2 files changed

+30
-34
lines changed

‎llvm/utils/TableGen/CompressInstEmitter.cpp‎

Lines changed: 18 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -85,16 +85,15 @@ using namespace llvm;
8585
namespace {
8686
class CompressInstEmitter {
8787
struct OpData {
88-
enum MapKind { Operand, Imm, Reg };
89-
MapKind Kind;
88+
enum MapKind { Operand, Imm, Reg } Kind;
9089
union {
9190
// Operand number mapped to.
92-
unsigned Operand;
91+
unsigned OpNo;
9392
// Integer immediate value.
94-
int64_t Imm;
93+
int64_t ImmVal;
9594
// Physical register.
96-
const Record *Reg;
97-
} Data;
95+
const Record *RegRec;
96+
};
9897
// Tied operand index within the instruction.
9998
int TiedOpIdx = -1;
10099
};
@@ -255,7 +254,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
255254
"' is not in register class '" +
256255
OpndRec->getName() + "'");
257256
OperandMap[OpNo].Kind = OpData::Reg;
258-
OperandMap[OpNo].Data.Reg = DI->getDef();
257+
OperandMap[OpNo].RegRec = DI->getDef();
259258
continue;
260259
}
261260
// Validate that Dag operand type matches the type defined in the
@@ -282,7 +281,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
282281
"operand expected a register!");
283282
// No pattern validation check possible for values of fixed immediate.
284283
OperandMap[OpNo].Kind = OpData::Imm;
285-
OperandMap[OpNo].Data.Imm = II->getValue();
284+
OperandMap[OpNo].ImmVal = II->getValue();
286285
LLVM_DEBUG(
287286
dbgs() << " Found immediate '" << II->getValue() << "' at "
288287
<< (IsSourceInst ? "input " : "output ")
@@ -403,9 +402,8 @@ void CompressInstEmitter::createInstOperandMapping(
403402
if (DestOperandMap[OpNo].Kind == OpData::Operand)
404403
// No need to fill the SourceOperandMap here since it was mapped to
405404
// destination operand 'TiedInstOpIdx' in a previous iteration.
406-
LLVM_DEBUG(dbgs() << " " << DestOperandMap[OpNo].Data.Operand
407-
<< " ====> " << OpNo
408-
<< " Dest operand tied with operand '"
405+
LLVM_DEBUG(dbgs() << " " << DestOperandMap[OpNo].OpNo << " ====> "
406+
<< OpNo << " Dest operand tied with operand '"
409407
<< TiedInstOpIdx << "'\n");
410408
++OpNo;
411409
continue;
@@ -430,8 +428,8 @@ void CompressInstEmitter::createInstOperandMapping(
430428
"Incorrect operand mapping detected!\n");
431429

432430
unsigned SourceOpNo = SourceOp->getValue().MIOpNo;
433-
DestOperandMap[OpNo].Data.Operand = SourceOpNo;
434-
SourceOperandMap[SourceOpNo].Data.Operand = OpNo;
431+
DestOperandMap[OpNo].OpNo = SourceOpNo;
432+
SourceOperandMap[SourceOpNo].OpNo = OpNo;
435433
LLVM_DEBUG(dbgs() << " " << SourceOpNo << " ====> " << OpNo << "\n");
436434
}
437435
}
@@ -774,11 +772,10 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
774772
CondStream.indent(8)
775773
<< "(MI.getOperand(" << OpNo << ").isImm()) &&\n"
776774
<< " (MI.getOperand(" << OpNo
777-
<< ").getImm() == " << SourceOperandMap[OpNo].Data.Imm
778-
<< ") &&\n";
775+
<< ").getImm() == " << SourceOperandMap[OpNo].ImmVal << ") &&\n";
779776
break;
780777
case OpData::Reg: {
781-
const Record *Reg = SourceOperandMap[OpNo].Data.Reg;
778+
const Record *Reg = SourceOperandMap[OpNo].RegRec;
782779
CondStream.indent(8) << "(MI.getOperand(" << OpNo << ").isReg()) &&\n"
783780
<< indent(8) << "(MI.getOperand(" << OpNo
784781
<< ").getReg() == " << TargetName
@@ -806,7 +803,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
806803

807804
switch (DestOperandMap[OpNo].Kind) {
808805
case OpData::Operand: {
809-
unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
806+
unsigned OpIdx = DestOperandMap[OpNo].OpNo;
810807
// Check that the operand in the Source instruction fits
811808
// the type for the Dest instruction.
812809
if (DestRec->isSubClassOf("RegisterClass") ||
@@ -862,7 +859,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
862859
DestRec, "MCOperandPredicate");
863860
CondStream.indent(8)
864861
<< ValidatorName << "("
865-
<< "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm
862+
<< "MCOperand::createImm(" << DestOperandMap[OpNo].Imm
866863
<< "), STI, " << Entry << ") &&\n";
867864
} else {
868865
unsigned Entry =
@@ -871,17 +868,17 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
871868
CondStream.indent(8)
872869
<< TargetName
873870
<< "ValidateMachineOperand(MachineOperand::CreateImm("
874-
<< DestOperandMap[OpNo].Data.Imm << "), &STI, " << Entry
871+
<< DestOperandMap[OpNo].ImmVal << "), &STI, " << Entry
875872
<< ") &&\n";
876873
}
877874
if (CompressOrUncompress)
878875
CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm("
879-
<< DestOperandMap[OpNo].Data.Imm << "));\n";
876+
<< DestOperandMap[OpNo].ImmVal << "));\n";
880877
} break;
881878
case OpData::Reg: {
882879
if (CompressOrUncompress) {
883880
// Fixed register has been validated at pattern validation time.
884-
const Record *Reg = DestOperandMap[OpNo].Data.Reg;
881+
const Record *Reg = DestOperandMap[OpNo].RegRec;
885882
CodeStream.indent(6)
886883
<< "OutInst.addOperand(MCOperand::createReg(" << TargetName
887884
<< "::" << Reg->getName() << "));\n";

‎llvm/utils/TableGen/PseudoLoweringEmitter.cpp‎

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -24,13 +24,12 @@ using namespace llvm;
2424
namespace {
2525
class PseudoLoweringEmitter {
2626
struct OpData {
27-
enum MapKind { Operand, Imm, Reg };
28-
MapKind Kind;
27+
enum MapKind { Operand, Imm, Reg } Kind;
2928
union {
30-
unsigned Operand; // Operand number mapped to.
31-
uint64_t Imm; // Integer immedate value.
32-
const Record *Reg; // Physical register.
33-
} Data;
29+
unsigned OpNo; // Operand number mapped to.
30+
uint64_t ImmVal; // Integer immedate value.
31+
const Record *RegRec; // Physical register.
32+
};
3433
};
3534
struct PseudoExpansion {
3635
CodeGenInstruction Source; // The source pseudo instruction definition.
@@ -80,7 +79,7 @@ void PseudoLoweringEmitter::addOperandMapping(
8079
DI->getDef()->getName() == "zero_reg") {
8180
auto &Entry = OperandMap[MIOpNo];
8281
Entry.Kind = OpData::Reg;
83-
Entry.Data.Reg = DI->getDef();
82+
Entry.RegRec = DI->getDef();
8483
return;
8584
}
8685

@@ -111,7 +110,7 @@ void PseudoLoweringEmitter::addOperandMapping(
111110
for (unsigned I = 0, E = NumOps; I != E; ++I) {
112111
auto &Entry = OperandMap[MIOpNo + I];
113112
Entry.Kind = OpData::Operand;
114-
Entry.Data.Operand = SrcOpnd.MIOperandNo + I;
113+
Entry.OpNo = SrcOpnd.MIOperandNo + I;
115114
}
116115

117116
LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << DagIdx
@@ -120,12 +119,12 @@ void PseudoLoweringEmitter::addOperandMapping(
120119
assert(NumOps == 1);
121120
auto &Entry = OperandMap[MIOpNo];
122121
Entry.Kind = OpData::Imm;
123-
Entry.Data.Imm = II->getValue();
122+
Entry.ImmVal = II->getValue();
124123
} else if (const auto *BI = dyn_cast<BitsInit>(DagArg)) {
125124
assert(NumOps == 1);
126125
auto &Entry = OperandMap[MIOpNo];
127126
Entry.Kind = OpData::Imm;
128-
Entry.Data.Imm = *BI->convertInitializerToInt();
127+
Entry.ImmVal = *BI->convertInitializerToInt();
129128
} else {
130129
llvm_unreachable("Unhandled pseudo-expansion argument type!");
131130
}
@@ -247,15 +246,15 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
247246
switch (Expansion.OperandMap[MIOpNo + i].Kind) {
248247
case OpData::Operand:
249248
o << " lowerOperand(MI->getOperand("
250-
<< Expansion.OperandMap[MIOpNo + i].Data.Operand << "), MCOp);\n"
249+
<< Expansion.OperandMap[MIOpNo + i].OpNo << "), MCOp);\n"
251250
<< " Inst.addOperand(MCOp);\n";
252251
break;
253252
case OpData::Imm:
254253
o << " Inst.addOperand(MCOperand::createImm("
255-
<< Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
254+
<< Expansion.OperandMap[MIOpNo + i].ImmVal << "));\n";
256255
break;
257256
case OpData::Reg: {
258-
const Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
257+
const Record *Reg = Expansion.OperandMap[MIOpNo + i].RegRec;
259258
o << " Inst.addOperand(MCOperand::createReg(";
260259
// "zero_reg" is special.
261260
if (Reg->getName() == "zero_reg")

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