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[AMDGPU] IGLP: Fix static variables
Replace global / class-level static variables with instance members and guarantee thread-safety.
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4 files changed

+106
-110
lines changed

4 files changed

+106
-110
lines changed

llvm/include/llvm/CodeGen/ScheduleDAG.h

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -734,7 +734,8 @@ class TargetRegisterInfo;
734734
/// Makes a DFS traversal and mark all nodes affected by the edge insertion.
735735
/// These nodes will later get new topological indexes by means of the Shift
736736
/// method.
737-
void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
737+
void DFS(const SUnit *SU, int UpperBound, bool &HasLoop,
738+
std::optional<SDep::Kind> OnlyDepKind = std::nullopt);
738739

739740
/// Reassigns topological indexes for the nodes in the DAG to
740741
/// preserve the topological ordering.
@@ -767,7 +768,9 @@ class TargetRegisterInfo;
767768
bool &Success);
768769

769770
/// Checks if \p SU is reachable from \p TargetSU.
770-
bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
771+
/// If OnlyDepKind is given, consider only dependencies of this kind.
772+
bool IsReachable(const SUnit *SU, const SUnit *TargetSU,
773+
std::optional<SDep::Kind> OnlyDepKind = std::nullopt);
771774

772775
/// Returns true if addPred(TargetSU, SU) creates a cycle.
773776
bool WillCreateCycle(SUnit *TargetSU, SUnit *SU);

llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -287,8 +287,10 @@ namespace llvm {
287287
}
288288

289289
/// IsReachable - Checks if SU is reachable from TargetSU.
290-
bool IsReachable(SUnit *SU, SUnit *TargetSU) {
291-
return Topo.IsReachable(SU, TargetSU);
290+
/// If OnlyDepKind is given, only dependencies of this kind are considered.
291+
bool IsReachable(SUnit *SU, SUnit *TargetSU,
292+
std::optional<SDep::Kind> OnlyDepKind = std::nullopt) {
293+
return Topo.IsReachable(SU, TargetSU, OnlyDepKind);
292294
}
293295

294296
/// Whether regions with a single MI should be scheduled.

llvm/lib/CodeGen/ScheduleDAG.cpp

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -570,7 +570,8 @@ void ScheduleDAGTopologicalSort::RemovePred(SUnit *M, SUnit *N) {
570570
}
571571

572572
void ScheduleDAGTopologicalSort::DFS(const SUnit *SU, int UpperBound,
573-
bool &HasLoop) {
573+
bool &HasLoop,
574+
std::optional<SDep::Kind> OnlyDepKind) {
574575
std::vector<const SUnit*> WorkList;
575576
WorkList.reserve(SUnits.size());
576577

@@ -580,6 +581,8 @@ void ScheduleDAGTopologicalSort::DFS(const SUnit *SU, int UpperBound,
580581
WorkList.pop_back();
581582
Visited.set(SU->NodeNum);
582583
for (const SDep &SuccDep : llvm::reverse(SU->Succs)) {
584+
if (OnlyDepKind && SuccDep.getKind() != *OnlyDepKind)
585+
continue;
583586
unsigned s = SuccDep.getSUnit()->NodeNum;
584587
// Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
585588
if (s >= Node2Index.size())
@@ -722,8 +725,9 @@ void ScheduleDAGTopologicalSort::AddSUnitWithoutPredecessors(const SUnit *SU) {
722725
Visited.resize(Node2Index.size());
723726
}
724727

725-
bool ScheduleDAGTopologicalSort::IsReachable(const SUnit *SU,
726-
const SUnit *TargetSU) {
728+
bool ScheduleDAGTopologicalSort::IsReachable(
729+
const SUnit *SU, const SUnit *TargetSU,
730+
std::optional<SDep::Kind> OnlyDepKind) {
727731
assert(TargetSU != nullptr && "Invalid target SUnit");
728732
assert(SU != nullptr && "Invalid SUnit");
729733
FixOrder();
@@ -737,7 +741,7 @@ bool ScheduleDAGTopologicalSort::IsReachable(const SUnit *SU,
737741
if (LowerBound < UpperBound) {
738742
Visited.reset();
739743
// There may be a path from TargetSU to SU. Check for it.
740-
DFS(TargetSU, UpperBound, HasLoop);
744+
DFS(TargetSU, UpperBound, HasLoop, OnlyDepKind);
741745
}
742746
return HasLoop;
743747
}

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