fixup! fixup! [clang][RISCV] Correct the SEW operand of indexed/fault only first segment intrinsics

4vtomat · 4vtomat · commit 0f7a59294e63 · 2024-10-14T21:30:43.000-07:00
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -177,7 +177,7 @@ static unsigned getIndexedLoadStorePtrIdx(const RVVIntrinsic *RVVI) {
   if (IRName.starts_with("vloxseg") || IRName.starts_with("vluxseg")) {
     bool NoPassthru =
         (RVVI->isMasked() && (RVVI->getPolicyAttrsBits() & RVV_VTA) &&
-         (RVVI->getPolicyAttrsBits() & RVV_VMA)) |
+         (RVVI->getPolicyAttrsBits() & RVV_VMA)) ||
         (!RVVI->isMasked() && (RVVI->getPolicyAttrsBits() & RVV_VTA));
     return RVVI->isMasked() ? NoPassthru ? 1 : 2 : NoPassthru ? 0 : 1;
   }

Original file line number	Diff line number	Diff line change
`@@ -177,7 +177,7 @@ static unsigned getIndexedLoadStorePtrIdx(const RVVIntrinsic *RVVI) {`
`177`	`177`	`if (IRName.starts_with("vloxseg") \|\| IRName.starts_with("vluxseg")) {`
`178`	`178`	`bool NoPassthru =`
`179`	`179`	`(RVVI->isMasked() && (RVVI->getPolicyAttrsBits() & RVV_VTA) &&`
`180`		`- (RVVI->getPolicyAttrsBits() & RVV_VMA)) \|`
	`180`	`+ (RVVI->getPolicyAttrsBits() & RVV_VMA)) \|\|`
`181`	`181`	`(!RVVI->isMasked() && (RVVI->getPolicyAttrsBits() & RVV_VTA));`
`182`	`182`	`return RVVI->isMasked() ? NoPassthru ? 1 : 2 : NoPassthru ? 0 : 1;`
`183`	`183`	`}`