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isScalar / isFixedVector
FPInfo: IRTranslator and CallLowering isScalar FPInfo: AMDGPUISel isScalar FPInfo: AMDGPURegBankLegalize isScalar FPInfo: AMDGPULegalizerInfo and Combiner isScalar FPInfo: CombinerHelper isScalar FPInfo: LegalizerHelper isScalar
1 parent 5b452bd commit 0f7b4f7

15 files changed

+117
-128
lines changed

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6821,7 +6821,7 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
68216821
LLT TrueTy = MRI.getType(Select->getTrueReg());
68226822

68236823
// We only do this combine for scalar boolean conditions.
6824-
if (CondTy != LLT::scalar(1))
6824+
if (!CondTy.isScalar(1))
68256825
return false;
68266826

68276827
if (TrueTy.isPointer())

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2105,7 +2105,7 @@ LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
21052105
const unsigned Offset = (I - 1) * PartSize;
21062106

21072107
Register SrcReg = MI.getOperand(I).getReg();
2108-
assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
2108+
assert(MRI.getType(SrcReg).isScalar(PartSize));
21092109

21102110
auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
21112111

@@ -6611,7 +6611,7 @@ LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx,
66116611
// If all finite floats fit into the narrowed integer type, we can just swap
66126612
// out the result type. This is practically only useful for conversions from
66136613
// half to at least 16-bits, so just handle the one case.
6614-
if (SrcTy.getScalarType() != LLT::scalar(16) ||
6614+
if (!SrcTy.getScalarType().isScalar(16) ||
66156615
NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u))
66166616
return UnableToLegalize;
66176617

@@ -7610,7 +7610,7 @@ LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
76107610
LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) {
76117611
auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
76127612

7613-
if (SrcTy == LLT::scalar(1)) {
7613+
if (SrcTy.isScalar(1)) {
76147614
auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
76157615
auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
76167616
MIRBuilder.buildSelect(Dst, Src, True, False);
@@ -9278,7 +9278,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
92789278

92799279
// The condition was potentially zero extended before, but we want a sign
92809280
// extended boolean.
9281-
if (MaskTy != LLT::scalar(1))
9281+
if (!MaskTy.isScalar(1))
92829282
MaskElt = MIRBuilder.buildSExtInReg(MaskTy, MaskElt, 1).getReg(0);
92839283

92849284
// Continue the sign extension (or truncate) to match the data type.

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
7272
if (TRI->isSGPRReg(MRI, PhysReg)) {
7373
LLT Ty = MRI.getType(ExtReg);
7474
LLT S32 = LLT::scalar(32);
75-
if (Ty != S32) {
75+
if (!Ty.isScalar(32)) {
7676
// FIXME: We should probably support readfirstlane intrinsics with all
7777
// legal 32-bit types.
7878
assert(Ty.getSizeInBits() == 32);

‎llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -409,7 +409,7 @@ static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
409409
const MachineInstr *Def = MRI.getVRegDef(Reg);
410410
if (Def->getOpcode() == TargetOpcode::G_FPEXT) {
411411
Register SrcReg = Def->getOperand(1).getReg();
412-
return MRI.getType(SrcReg) == LLT::scalar(16);
412+
return MRI.getType(SrcReg).isScalar(16);
413413
}
414414

415415
if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
@@ -428,7 +428,7 @@ bool AMDGPUCombinerHelper::matchExpandPromotedF16FMed3(MachineInstr &MI,
428428
Register Src2) const {
429429
assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC);
430430
Register SrcReg = MI.getOperand(1).getReg();
431-
if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::scalar(32))
431+
if (!MRI.hasOneNonDBGUse(SrcReg) || !MRI.getType(SrcReg).isScalar(32))
432432
return false;
433433

434434
return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) &&

‎llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ DivergenceLoweringHelper::DivergenceLoweringHelper(
8787

8888
// _(s1) -> SReg_32/64(s1)
8989
void DivergenceLoweringHelper::markAsLaneMask(Register DstReg) const {
90-
assert(MRI->getType(DstReg) == LLT::scalar(1));
90+
assert(MRI->getType(DstReg).isScalar(1));
9191

9292
if (MRI->getRegClassOrNull(DstReg)) {
9393
if (MRI->constrainRegClass(DstReg, ST->getBoolRC()))
@@ -100,13 +100,11 @@ void DivergenceLoweringHelper::markAsLaneMask(Register DstReg) const {
100100

101101
void DivergenceLoweringHelper::getCandidatesForLowering(
102102
SmallVectorImpl<MachineInstr *> &Vreg1Phis) const {
103-
LLT S1 = LLT::scalar(1);
104-
105103
// Add divergent i1 phis to the list
106104
for (MachineBasicBlock &MBB : *MF) {
107105
for (MachineInstr &MI : MBB.phis()) {
108106
Register Dst = MI.getOperand(0).getReg();
109-
if (MRI->getType(Dst) == S1 && MUI->isDivergent(Dst))
107+
if (MRI->getType(Dst).isScalar(1) && MUI->isDivergent(Dst))
110108
Vreg1Phis.push_back(&MI);
111109
}
112110
}

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 19 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
105105
MachineOperand &Src = MI.getOperand(1);
106106

107107
// TODO: This should be legalized to s32 if needed
108-
if (MRI->getType(Dst.getReg()) == LLT::scalar(1))
108+
if (MRI->getType(Dst.getReg()).isScalar(1))
109109
return false;
110110

111111
const TargetRegisterClass *DstRC
@@ -293,7 +293,7 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
293293
// - divergent S1 G_PHI should go through lane mask merging algorithm
294294
// and be fully inst-selected in AMDGPUGlobalISelDivergenceLowering
295295
// - uniform S1 G_PHI should be lowered into S32 G_PHI in AMDGPURegBankSelect
296-
if (DefTy == LLT::scalar(1))
296+
if (DefTy.isScalar(1))
297297
return false;
298298

299299
// TODO: Verify this doesn't have insane operands (i.e. VGPR to SGPR copy)
@@ -733,9 +733,8 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
733733
// Selection logic below is for V2S16 only.
734734
// For G_BUILD_VECTOR_TRUNC, additionally check that the operands are s32.
735735
Register Dst = MI.getOperand(0).getReg();
736-
if (MRI->getType(Dst) != LLT::fixed_vector(2, 16) ||
737-
(MI.getOpcode() == AMDGPU::G_BUILD_VECTOR_TRUNC &&
738-
SrcTy != LLT::scalar(32)))
736+
if (!MRI->getType(Dst).isFixedVector(2, 16) ||
737+
(MI.getOpcode() == AMDGPU::G_BUILD_VECTOR_TRUNC && !SrcTy.isScalar(32)))
739738
return selectImpl(MI, *CoverageInfo);
740739

741740
const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI);
@@ -1073,9 +1072,9 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
10731072

10741073
LLT Ty = MRI->getType(Dst0);
10751074
unsigned Opc;
1076-
if (Ty == LLT::scalar(32))
1075+
if (Ty.isScalar(32))
10771076
Opc = AMDGPU::V_DIV_SCALE_F32_e64;
1078-
else if (Ty == LLT::scalar(64))
1077+
else if (Ty.isScalar(64))
10791078
Opc = AMDGPU::V_DIV_SCALE_F64_e64;
10801079
else
10811080
return false;
@@ -2390,11 +2389,10 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
23902389
Register SrcReg = I.getOperand(1).getReg();
23912390
const LLT DstTy = MRI->getType(DstReg);
23922391
const LLT SrcTy = MRI->getType(SrcReg);
2393-
const LLT S1 = LLT::scalar(1);
23942392

23952393
const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
23962394
const RegisterBank *DstRB;
2397-
if (DstTy == S1) {
2395+
if (DstTy.isScalar(1)) {
23982396
// This is a special case. We don't treat s1 for legalization artifacts as
23992397
// vcc booleans.
24002398
DstRB = SrcRB;
@@ -2432,7 +2430,7 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
24322430
return true;
24332431
}
24342432

2435-
if (DstTy == LLT::fixed_vector(2, 16) && SrcTy == LLT::fixed_vector(2, 32)) {
2433+
if (DstTy.isFixedVector(2, 16) && SrcTy.isFixedVector(2, 32)) {
24362434
MachineBasicBlock *MBB = I.getParent();
24372435
const DebugLoc &DL = I.getDebugLoc();
24382436

@@ -2724,8 +2722,7 @@ static bool isExtractHiElt(MachineRegisterInfo &MRI, Register In,
27242722
if (Shuffle->getOpcode() != AMDGPU::G_SHUFFLE_VECTOR)
27252723
return false;
27262724

2727-
assert(MRI.getType(Shuffle->getOperand(0).getReg()) ==
2728-
LLT::fixed_vector(2, 16));
2725+
assert(MRI.getType(Shuffle->getOperand(0).getReg()).isFixedVector(2, 16));
27292726

27302727
ArrayRef<int> Mask = Shuffle->getOperand(3).getShuffleMask();
27312728
assert(Mask.size() == 2);
@@ -2749,8 +2746,7 @@ bool AMDGPUInstructionSelector::selectG_FPEXT(MachineInstr &I) const {
27492746

27502747
Register Src = I.getOperand(1).getReg();
27512748

2752-
if (MRI->getType(Dst) == LLT::scalar(32) &&
2753-
MRI->getType(Src) == LLT::scalar(16)) {
2749+
if (MRI->getType(Dst).isScalar(32) && MRI->getType(Src).isScalar(16)) {
27542750
if (isExtractHiElt(*MRI, Src, Src)) {
27552751
MachineBasicBlock *BB = I.getParent();
27562752
BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_CVT_HI_F32_F16), Dst)
@@ -2778,7 +2774,7 @@ bool AMDGPUInstructionSelector::selectG_FNEG(MachineInstr &MI) const {
27782774
Register Dst = MI.getOperand(0).getReg();
27792775
const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);
27802776
if (DstRB->getID() != AMDGPU::SGPRRegBankID ||
2781-
MRI->getType(Dst) != LLT::scalar(64))
2777+
!MRI->getType(Dst).isScalar(64))
27822778
return false;
27832779

27842780
Register Src = MI.getOperand(1).getReg();
@@ -2824,7 +2820,7 @@ bool AMDGPUInstructionSelector::selectG_FABS(MachineInstr &MI) const {
28242820
Register Dst = MI.getOperand(0).getReg();
28252821
const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);
28262822
if (DstRB->getID() != AMDGPU::SGPRRegBankID ||
2827-
MRI->getType(Dst) != LLT::scalar(64))
2823+
!MRI->getType(Dst).isScalar(64))
28282824
return false;
28292825

28302826
Register Src = MI.getOperand(1).getReg();
@@ -2996,7 +2992,7 @@ bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
29962992
// RegBankSelect knows what it's doing if the branch condition is scc, even
29972993
// though it currently does not.
29982994
if (!isVCC(CondReg, *MRI)) {
2999-
if (MRI->getType(CondReg) != LLT::scalar(32))
2995+
if (!MRI->getType(CondReg).isScalar(32))
30002996
return false;
30012997

30022998
CondPhysReg = AMDGPU::SCC;
@@ -3459,15 +3455,15 @@ bool AMDGPUInstructionSelector::selectBufferLoadLds(MachineInstr &MI) const {
34593455
static Register matchZeroExtendFromS32(MachineRegisterInfo &MRI, Register Reg) {
34603456
Register ZExtSrc;
34613457
if (mi_match(Reg, MRI, m_GZExt(m_Reg(ZExtSrc))))
3462-
return MRI.getType(ZExtSrc) == LLT::scalar(32) ? ZExtSrc : Register();
3458+
return MRI.getType(ZExtSrc).isScalar(32) ? ZExtSrc : Register();
34633459

34643460
// Match legalized form %zext = G_MERGE_VALUES (s32 %x), (s32 0)
34653461
const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
34663462
if (Def->getOpcode() != AMDGPU::G_MERGE_VALUES)
34673463
return Register();
34683464

34693465
assert(Def->getNumOperands() == 3 &&
3470-
MRI.getType(Def->getOperand(0).getReg()) == LLT::scalar(64));
3466+
MRI.getType(Def->getOperand(0).getReg()).isScalar(64));
34713467
if (mi_match(Def->getOperand(2).getReg(), MRI, m_ZeroInt())) {
34723468
return Def->getOperand(1).getReg();
34733469
}
@@ -4058,7 +4054,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
40584054
// This is a workaround. For extension from type i1, `selectImpl()` uses
40594055
// patterns from TD file and generates an illegal VGPR to SGPR COPY as type
40604056
// i1 can only be hold in a SGPR class.
4061-
if (MRI->getType(I.getOperand(1).getReg()) != LLT::scalar(1) &&
4057+
if (!MRI->getType(I.getOperand(1).getReg()).isScalar(1) &&
40624058
selectImpl(I, *CoverageInfo))
40634059
return true;
40644060
return selectG_SZA_EXT(I);
@@ -4291,7 +4287,7 @@ AMDGPUInstructionSelector::selectVOP3PModsImpl(
42914287
if (MI->getOpcode() == AMDGPU::G_FNEG &&
42924288
// It's possible to see an f32 fneg here, but unlikely.
42934289
// TODO: Treat f32 fneg as only high bit.
4294-
MRI.getType(Src) == LLT::fixed_vector(2, 16)) {
4290+
MRI.getType(Src).isFixedVector(2, 16)) {
42954291
Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
42964292
Src = MI->getOperand(1).getReg();
42974293
MI = MRI.getVRegDef(Src);
@@ -5789,7 +5785,7 @@ AMDGPUInstructionSelector::selectSMRDBufferSgprImm(MachineOperand &Root) const {
57895785
if (!EncodedOffset)
57905786
return std::nullopt;
57915787

5792-
assert(MRI->getType(SOffset) == LLT::scalar(32));
5788+
assert(MRI->getType(SOffset).isScalar(32));
57935789
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },
57945790
[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}};
57955791
}
@@ -5804,7 +5800,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
58045800
std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
58055801

58065802
if (mi_match(Src, *MRI, m_GFPExt(m_Reg(Src)))) {
5807-
assert(MRI->getType(Src) == LLT::scalar(16));
5803+
assert(MRI->getType(Src).isScalar(16));
58085804

58095805
// Only change Src if src modifier could be gained. In such cases new Src
58105806
// could be sgpr but this does not violate constant bus restriction for

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -278,7 +278,7 @@ static LegalityPredicate elementTypeIsLegal(unsigned TypeIdx) {
278278
if (!QueryTy.isVector())
279279
return false;
280280
const LLT EltTy = QueryTy.getElementType();
281-
return EltTy == LLT::scalar(16) || EltTy.getSizeInBits() >= 32;
281+
return EltTy.isScalar(16) || EltTy.getSizeInBits() >= 32;
282282
};
283283
}
284284

@@ -2451,7 +2451,7 @@ bool AMDGPULegalizerInfo::legalizeFroundeven(MachineInstr &MI,
24512451
MachineIRBuilder &B) const {
24522452
Register Src = MI.getOperand(1).getReg();
24532453
LLT Ty = MRI.getType(Src);
2454-
assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
2454+
assert(Ty.isFloat() && Ty.getSizeInBits() == 64);
24552455

24562456
APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
24572457
APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
@@ -2480,7 +2480,7 @@ bool AMDGPULegalizerInfo::legalizeFceil(
24802480
const LLT S64 = LLT::scalar(64);
24812481

24822482
Register Src = MI.getOperand(1).getReg();
2483-
assert(MRI.getType(Src) == S64);
2483+
assert(MRI.getType(Src).isFloat(64));
24842484

24852485
// result = trunc(src)
24862486
// if (src > 0.0 && src != result)

‎llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -213,7 +213,7 @@ bool AMDGPUPostLegalizerCombinerImpl::matchUCharToFloat(
213213
// types are legalized. v4i8 -> v4f32 is probably the only case to worry
214214
// about in practice.
215215
LLT Ty = MRI.getType(DstReg);
216-
if (Ty == LLT::scalar(32) || Ty == LLT::scalar(16)) {
216+
if (Ty.isScalar(32) || Ty.isScalar(16)) {
217217
Register SrcReg = MI.getOperand(1).getReg();
218218
unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
219219
assert(SrcSize == 16 || SrcSize == 32 || SrcSize == 64);
@@ -349,7 +349,7 @@ void AMDGPUPostLegalizerCombinerImpl::applyCvtF32UByteN(
349349
const LLT S32 = LLT::scalar(32);
350350
Register CvtSrc = MatchInfo.CvtVal;
351351
LLT SrcTy = MRI.getType(MatchInfo.CvtVal);
352-
if (SrcTy != S32) {
352+
if (!SrcTy.isScalar(32)) {
353353
assert(SrcTy.isScalar() && SrcTy.getSizeInBits() >= 8);
354354
CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0);
355355
}
@@ -418,7 +418,7 @@ bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64(
418418
MachineInstr &MI, unsigned &NewOpcode) const {
419419
Register Src0 = MI.getOperand(1).getReg();
420420
Register Src1 = MI.getOperand(2).getReg();
421-
if (MRI.getType(Src0) != LLT::scalar(64))
421+
if (!MRI.getType(Src0).isScalar(64))
422422
return false;
423423

424424
if (KB->getKnownBits(Src1).countMinLeadingZeros() >= 32 &&

‎llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -119,11 +119,11 @@ bool AMDGPUPreLegalizerCombinerImpl::matchClampI64ToI16(
119119

120120
// Try to find a pattern where an i64 value should get clamped to short.
121121
const LLT SrcType = MRI.getType(MI.getOperand(1).getReg());
122-
if (SrcType != LLT::scalar(64))
122+
if (!SrcType.isScalar(64))
123123
return false;
124124

125125
const LLT DstType = MRI.getType(MI.getOperand(0).getReg());
126-
if (DstType != LLT::scalar(16))
126+
if (!DstType.isScalar(16))
127127
return false;
128128

129129
Register Base;
@@ -177,8 +177,7 @@ void AMDGPUPreLegalizerCombinerImpl::applyClampI64ToI16(
177177
MachineInstr &MI, const ClampI64ToI16MatchInfo &MatchInfo) const {
178178

179179
Register Src = MatchInfo.Origin;
180-
assert(MI.getParent()->getParent()->getRegInfo().getType(Src) ==
181-
LLT::scalar(64));
180+
assert(MI.getParent()->getParent()->getRegInfo().getType(Src).isScalar(64));
182181
const LLT S32 = LLT::scalar(32);
183182

184183
auto Unmerge = B.buildUnmerge(S32, Src);

‎llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@ bool AMDGPURegBankCombinerImpl::matchIntMinMaxToMed3(
195195

196196
// med3 for i16 is only available on gfx9+, and not available for v2i16.
197197
LLT Ty = MRI.getType(Dst);
198-
if ((Ty != LLT::scalar(16) || !STI.hasMed3_16()) && Ty != LLT::scalar(32))
198+
if ((!Ty.isScalar(16) || !STI.hasMed3_16()) && !Ty.isScalar(32))
199199
return false;
200200

201201
MinMaxMedOpc OpcodeTriple = getMinMaxPair(MI.getOpcode());
@@ -238,7 +238,7 @@ bool AMDGPURegBankCombinerImpl::matchFPMinMaxToMed3(
238238
LLT Ty = MRI.getType(Dst);
239239

240240
// med3 for f16 is only available on gfx9+, and not available for v2f16.
241-
if ((Ty != LLT::scalar(16) || !STI.hasMed3_16()) && Ty != LLT::scalar(32))
241+
if ((!Ty.isScalar(16) || !STI.hasMed3_16()) && !Ty.isScalar(32))
242242
return false;
243243

244244
auto OpcodeTriple = getMinMaxPair(MI.getOpcode());

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