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Revert "[SPIRV] Add explicit layout (#135789)"
Breaks bot: https://lab.llvm.org/buildbot/#/builders/24/builds/8092 This reverts commit 492ad84.
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7 files changed

+124
-523
lines changed

7 files changed

+124
-523
lines changed

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp‎

Lines changed: 105 additions & 188 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h‎

Lines changed: 9 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -90,14 +90,14 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
9090
// Add a new OpTypeXXX instruction without checking for duplicates.
9191
SPIRVType *createSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
9292
SPIRV::AccessQualifier::AccessQualifier AQ,
93-
bool ExplicitLayoutRequired, bool EmitIR);
93+
bool EmitIR);
9494
SPIRVType *findSPIRVType(const Type *Ty, MachineIRBuilder &MIRBuilder,
9595
SPIRV::AccessQualifier::AccessQualifier accessQual,
96-
bool ExplicitLayoutRequired, bool EmitIR);
96+
bool EmitIR);
9797
SPIRVType *
9898
restOfCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
9999
SPIRV::AccessQualifier::AccessQualifier AccessQual,
100-
bool ExplicitLayoutRequired, bool EmitIR);
100+
bool EmitIR);
101101

102102
// Internal function creating the an OpType at the correct position in the
103103
// function by tweaking the passed "MIRBuilder" insertion point and restoring
@@ -298,19 +298,10 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
298298
// EmitIR controls if we emit GMIR or SPV constants (e.g. for array sizes)
299299
// because this method may be called from InstructionSelector and we don't
300300
// want to emit extra IR instructions there.
301-
SPIRVType *getOrCreateSPIRVType(const Type *Type, MachineInstr &I,
302-
SPIRV::AccessQualifier::AccessQualifier AQ,
303-
bool EmitIR) {
304-
MachineIRBuilder MIRBuilder(I);
305-
return getOrCreateSPIRVType(Type, MIRBuilder, AQ, EmitIR);
306-
}
307-
308301
SPIRVType *getOrCreateSPIRVType(const Type *Type,
309302
MachineIRBuilder &MIRBuilder,
310303
SPIRV::AccessQualifier::AccessQualifier AQ,
311-
bool EmitIR) {
312-
return getOrCreateSPIRVType(Type, MIRBuilder, AQ, false, EmitIR);
313-
}
304+
bool EmitIR);
314305

315306
const Type *getTypeForSPIRVType(const SPIRVType *Ty) const {
316307
auto Res = SPIRVToLLVMType.find(Ty);
@@ -373,10 +364,6 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
373364
// opcode (e.g. OpTypeBool, or OpTypeVector %x 4, where %x is OpTypeBool).
374365
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const;
375366

376-
// Returns true if `Type` is a resource type. This could be an image type
377-
// or a struct for a buffer decorated with the block decoration.
378-
bool isResourceType(SPIRVType *Type) const;
379-
380367
// Return number of elements in a vector if the argument is associated with
381368
// a vector type. Return 1 for a scalar type, and 0 for a missing type.
382369
unsigned getScalarOrVectorComponentCount(Register VReg) const;
@@ -427,11 +414,6 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
427414
const Type *adjustIntTypeByWidth(const Type *Ty) const;
428415
unsigned adjustOpTypeIntWidth(unsigned Width) const;
429416

430-
SPIRVType *getOrCreateSPIRVType(const Type *Type,
431-
MachineIRBuilder &MIRBuilder,
432-
SPIRV::AccessQualifier::AccessQualifier AQ,
433-
bool ExplicitLayoutRequired, bool EmitIR);
434-
435417
SPIRVType *getOpTypeInt(unsigned Width, MachineIRBuilder &MIRBuilder,
436418
bool IsSigned = false);
437419

@@ -443,15 +425,14 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
443425
MachineIRBuilder &MIRBuilder);
444426

445427
SPIRVType *getOpTypeArray(uint32_t NumElems, SPIRVType *ElemType,
446-
MachineIRBuilder &MIRBuilder,
447-
bool ExplicitLayoutRequired, bool EmitIR);
428+
MachineIRBuilder &MIRBuilder, bool EmitIR);
448429

449430
SPIRVType *getOpTypeOpaque(const StructType *Ty,
450431
MachineIRBuilder &MIRBuilder);
451432

452433
SPIRVType *getOpTypeStruct(const StructType *Ty, MachineIRBuilder &MIRBuilder,
453434
SPIRV::AccessQualifier::AccessQualifier AccQual,
454-
bool ExplicitLayoutRequired, bool EmitIR);
435+
bool EmitIR);
455436

456437
SPIRVType *getOpTypePointer(SPIRV::StorageClass::StorageClass SC,
457438
SPIRVType *ElemType, MachineIRBuilder &MIRBuilder,
@@ -494,12 +475,6 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
494475
MachineIRBuilder &MIRBuilder,
495476
SPIRV::StorageClass::StorageClass SC);
496477

497-
void addStructOffsetDecorations(Register Reg, StructType *Ty,
498-
MachineIRBuilder &MIRBuilder);
499-
void addArrayStrideDecorations(Register Reg, Type *ElementType,
500-
MachineIRBuilder &MIRBuilder);
501-
bool hasBlockDecoration(SPIRVType *Type) const;
502-
503478
public:
504479
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder,
505480
SPIRVType *SpvType, bool EmitIR,
@@ -570,6 +545,9 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
570545
SPIRVType *getOrCreateSPIRVVectorType(SPIRVType *BaseType,
571546
unsigned NumElements, MachineInstr &I,
572547
const SPIRVInstrInfo &TII);
548+
SPIRVType *getOrCreateSPIRVArrayType(SPIRVType *BaseType,
549+
unsigned NumElements, MachineInstr &I,
550+
const SPIRVInstrInfo &TII);
573551

574552
// Returns a pointer to a SPIR-V pointer type with the given base type and
575553
// storage class. The base type will be translated to a SPIR-V type, and the

‎llvm/lib/Target/SPIRV/SPIRVIRMapping.h‎

Lines changed: 5 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,6 @@ enum SpecialTypeKind {
6666
STK_Value,
6767
STK_MachineInstr,
6868
STK_VkBuffer,
69-
STK_ExplictLayoutType,
7069
STK_Last = -1
7170
};
7271

@@ -151,11 +150,6 @@ inline IRHandle irhandle_vkbuffer(const Type *ElementType,
151150
SpecialTypeKind::STK_VkBuffer);
152151
}
153152

154-
inline IRHandle irhandle_explict_layout_type(const Type *Ty) {
155-
const Type *WrpTy = unifyPtrType(Ty);
156-
return irhandle_ptr(WrpTy, Ty->getTypeID(), STK_ExplictLayoutType);
157-
}
158-
159153
inline IRHandle handle(const Type *Ty) {
160154
const Type *WrpTy = unifyPtrType(Ty);
161155
return irhandle_ptr(WrpTy, Ty->getTypeID(), STK_Type);
@@ -169,10 +163,6 @@ inline IRHandle handle(const MachineInstr *KeyMI) {
169163
return irhandle_ptr(KeyMI, SPIRV::to_hash(KeyMI), STK_MachineInstr);
170164
}
171165

172-
inline bool type_has_layout_decoration(const Type *T) {
173-
return (isa<StructType>(T) || isa<ArrayType>(T));
174-
}
175-
176166
} // namespace SPIRV
177167

178168
// Bi-directional mappings between LLVM entities and (v-reg, machine function)
@@ -248,49 +238,14 @@ class SPIRVIRMapping {
248238
return findMI(SPIRV::irhandle_pointee(PointeeTy, AddressSpace), MF);
249239
}
250240

251-
bool add(const Value *V, const MachineInstr *MI) {
252-
return add(SPIRV::handle(V), MI);
253-
}
254-
255-
bool add(const Type *T, bool RequiresExplicitLayout, const MachineInstr *MI) {
256-
if (RequiresExplicitLayout && SPIRV::type_has_layout_decoration(T)) {
257-
return add(SPIRV::irhandle_explict_layout_type(T), MI);
258-
}
259-
return add(SPIRV::handle(T), MI);
260-
}
261-
262-
bool add(const MachineInstr *Obj, const MachineInstr *MI) {
241+
template <typename T> bool add(const T *Obj, const MachineInstr *MI) {
263242
return add(SPIRV::handle(Obj), MI);
264243
}
265-
266-
Register find(const Value *V, const MachineFunction *MF) {
267-
return find(SPIRV::handle(V), MF);
268-
}
269-
270-
Register find(const Type *T, bool RequiresExplicitLayout,
271-
const MachineFunction *MF) {
272-
if (RequiresExplicitLayout && SPIRV::type_has_layout_decoration(T))
273-
return find(SPIRV::irhandle_explict_layout_type(T), MF);
274-
return find(SPIRV::handle(T), MF);
275-
}
276-
277-
Register find(const MachineInstr *MI, const MachineFunction *MF) {
278-
return find(SPIRV::handle(MI), MF);
279-
}
280-
281-
const MachineInstr *findMI(const Value *Obj, const MachineFunction *MF) {
282-
return findMI(SPIRV::handle(Obj), MF);
283-
}
284-
285-
const MachineInstr *findMI(const Type *T, bool RequiresExplicitLayout,
286-
const MachineFunction *MF) {
287-
if (RequiresExplicitLayout && SPIRV::type_has_layout_decoration(T))
288-
return findMI(SPIRV::irhandle_explict_layout_type(T), MF);
289-
return findMI(SPIRV::handle(T), MF);
244+
template <typename T> Register find(const T *Obj, const MachineFunction *MF) {
245+
return find(SPIRV::handle(Obj), MF);
290246
}
291-
292-
const MachineInstr *findMI(const MachineInstr *Obj,
293-
const MachineFunction *MF) {
247+
template <typename T>
248+
const MachineInstr *findMI(const T *Obj, const MachineFunction *MF) {
294249
return findMI(SPIRV::handle(Obj), MF);
295250
}
296251
};

‎llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp‎

Lines changed: 0 additions & 94 deletions
Original file line numberDiff line numberDiff line change
@@ -25,42 +25,6 @@
2525

2626
using namespace llvm;
2727

28-
// Returns true of the types logically match, as defined in
29-
// https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpCopyLogical.
30-
static bool typesLogicallyMatch(const SPIRVType *Ty1, const SPIRVType *Ty2,
31-
SPIRVGlobalRegistry &GR) {
32-
if (Ty1->getOpcode() != Ty2->getOpcode())
33-
return false;
34-
35-
if (Ty1->getNumOperands() != Ty2->getNumOperands())
36-
return false;
37-
38-
if (Ty1->getOpcode() == SPIRV::OpTypeArray) {
39-
// Array must have the same size.
40-
if (Ty1->getOperand(2).getReg() != Ty2->getOperand(2).getReg())
41-
return false;
42-
43-
SPIRVType *ElemType1 = GR.getSPIRVTypeForVReg(Ty1->getOperand(1).getReg());
44-
SPIRVType *ElemType2 = GR.getSPIRVTypeForVReg(Ty2->getOperand(1).getReg());
45-
return ElemType1 == ElemType2 ||
46-
typesLogicallyMatch(ElemType1, ElemType2, GR);
47-
}
48-
49-
if (Ty1->getOpcode() == SPIRV::OpTypeStruct) {
50-
for (unsigned I = 1; I < Ty1->getNumOperands(); I++) {
51-
SPIRVType *ElemType1 =
52-
GR.getSPIRVTypeForVReg(Ty1->getOperand(I).getReg());
53-
SPIRVType *ElemType2 =
54-
GR.getSPIRVTypeForVReg(Ty2->getOperand(I).getReg());
55-
if (ElemType1 != ElemType2 &&
56-
!typesLogicallyMatch(ElemType1, ElemType2, GR))
57-
return false;
58-
}
59-
return true;
60-
}
61-
return false;
62-
}
63-
6428
unsigned SPIRVTargetLowering::getNumRegistersForCallingConv(
6529
LLVMContext &Context, CallingConv::ID CC, EVT VT) const {
6630
// This code avoids CallLowering fail inside getVectorTypeBreakdown
@@ -410,9 +374,6 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
410374
// implies that %Op is a pointer to <ResType>
411375
case SPIRV::OpLoad:
412376
// OpLoad <ResType>, ptr %Op implies that %Op is a pointer to <ResType>
413-
if (enforcePtrTypeCompatibility(MI, 2, 0))
414-
break;
415-
416377
validatePtrTypes(STI, MRI, GR, MI, 2,
417378
GR.getSPIRVTypeForVReg(MI.getOperand(0).getReg()));
418379
break;
@@ -570,58 +531,3 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
570531
ProcessedMF.insert(&MF);
571532
TargetLowering::finalizeLowering(MF);
572533
}
573-
574-
// Modifies either operand PtrOpIdx or OpIdx so that the pointee type of
575-
// PtrOpIdx matches the type for operand OpIdx. Returns true if they already
576-
// match or if the instruction was modified to make them match.
577-
bool SPIRVTargetLowering::enforcePtrTypeCompatibility(
578-
MachineInstr &I, unsigned int PtrOpIdx, unsigned int OpIdx) const {
579-
SPIRVGlobalRegistry &GR = *STI.getSPIRVGlobalRegistry();
580-
SPIRVType *PtrType = GR.getResultType(I.getOperand(PtrOpIdx).getReg());
581-
SPIRVType *PointeeType = GR.getPointeeType(PtrType);
582-
SPIRVType *OpType = GR.getResultType(I.getOperand(OpIdx).getReg());
583-
584-
if (PointeeType == OpType)
585-
return true;
586-
587-
if (typesLogicallyMatch(PointeeType, OpType, GR)) {
588-
// Apply OpCopyLogical to OpIdx.
589-
if (I.getOperand(OpIdx).isDef() &&
590-
insertLogicalCopyOnResult(I, PointeeType)) {
591-
return true;
592-
}
593-
594-
llvm_unreachable("Unable to add OpCopyLogical yet.");
595-
return false;
596-
}
597-
598-
return false;
599-
}
600-
601-
bool SPIRVTargetLowering::insertLogicalCopyOnResult(
602-
MachineInstr &I, SPIRVType *NewResultType) const {
603-
MachineRegisterInfo *MRI = &I.getMF()->getRegInfo();
604-
SPIRVGlobalRegistry &GR = *STI.getSPIRVGlobalRegistry();
605-
606-
Register NewResultReg =
607-
createVirtualRegister(NewResultType, &GR, MRI, *I.getMF());
608-
Register NewTypeReg = GR.getSPIRVTypeID(NewResultType);
609-
610-
assert(std::distance(I.defs().begin(), I.defs().end()) == 1 &&
611-
"Expected only one def");
612-
MachineOperand &OldResult = *I.defs().begin();
613-
Register OldResultReg = OldResult.getReg();
614-
MachineOperand &OldType = *I.uses().begin();
615-
Register OldTypeReg = OldType.getReg();
616-
617-
OldResult.setReg(NewResultReg);
618-
OldType.setReg(NewTypeReg);
619-
620-
MachineIRBuilder MIB(*I.getNextNode());
621-
return MIB.buildInstr(SPIRV::OpCopyLogical)
622-
.addDef(OldResultReg)
623-
.addUse(OldTypeReg)
624-
.addUse(NewResultReg)
625-
.constrainAllUses(*STI.getInstrInfo(), *STI.getRegisterInfo(),
626-
*STI.getRegBankInfo());
627-
}

‎llvm/lib/Target/SPIRV/SPIRVISelLowering.h‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -71,11 +71,6 @@ class SPIRVTargetLowering : public TargetLowering {
7171
EVT ConditionVT) const override {
7272
return ConditionVT.getSimpleVT();
7373
}
74-
75-
bool enforcePtrTypeCompatibility(MachineInstr &I, unsigned PtrOpIdx,
76-
unsigned OpIdx) const;
77-
bool insertLogicalCopyOnResult(MachineInstr &I,
78-
SPIRVType *NewResultType) const;
7974
};
8075
} // namespace llvm
8176

‎llvm/test/CodeGen/SPIRV/hlsl-resources/StructuredBuffer.ll‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -11,18 +11,17 @@ declare target("spirv.VulkanBuffer", [0 x i32], 12, 1) @llvm.spv.resource.handle
1111

1212
; CHECK: OpDecorate [[BufferVar:%.+]] DescriptorSet 0
1313
; CHECK: OpDecorate [[BufferVar]] Binding 0
14-
; CHECK: OpMemberDecorate [[BufferType:%.+]] 0 Offset 0
15-
; CHECK: OpDecorate [[BufferType]] Block
14+
; CHECK: OpDecorate [[BufferType:%.+]] Block
15+
; CHECK: OpMemberDecorate [[BufferType]] 0 Offset 0
1616
; CHECK: OpMemberDecorate [[BufferType]] 0 NonWritable
1717
; CHECK: OpDecorate [[RWBufferVar:%.+]] DescriptorSet 0
1818
; CHECK: OpDecorate [[RWBufferVar]] Binding 1
19-
; CHECK: OpDecorate [[ArrayType:%.+]] ArrayStride 4
20-
; CHECK: OpMemberDecorate [[RWBufferType:%.+]] 0 Offset 0
21-
; CHECK: OpDecorate [[RWBufferType]] Block
19+
; CHECK: OpDecorate [[RWBufferType:%.+]] Block
20+
; CHECK: OpMemberDecorate [[RWBufferType]] 0 Offset 0
2221

2322

2423
; CHECK: [[int:%[0-9]+]] = OpTypeInt 32 0
25-
; CHECK: [[ArrayType]] = OpTypeRuntimeArray
24+
; CHECK: [[ArrayType:%.+]] = OpTypeRuntimeArray
2625
; CHECK: [[RWBufferType]] = OpTypeStruct [[ArrayType]]
2726
; CHECK: [[RWBufferPtrType:%.+]] = OpTypePointer StorageBuffer [[RWBufferType]]
2827
; CHECK: [[BufferType]] = OpTypeStruct [[ArrayType]]

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