fixup! ensure we only check for users of virtual registers. Don't optimize addi with x0.

Author: topperc

llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp

@@ -103,6 +103,9 @@ bool RISCVFoldMemOffset::foldOffset(
     Register Reg = Worklist.front();
     Worklist.pop();
 
+    if (!Reg.isVirtual())
+      return false;
+
     for (auto &User : MRI.use_nodbg_instructions(Reg)) {
       FoldableOffset Offset;
 
@@ -250,6 +253,10 @@ bool RISCVFoldMemOffset::runOnMachineFunction(MachineFunction &MF) {
       if (!MI.getOperand(1).isReg() || !MI.getOperand(2).isImm())
         continue;
 
+      // Ignore 'li'.
+      if (MI.getOperand(1).getReg() == RISCV::X0)
+        continue;
+
       int64_t Offset = MI.getOperand(2).getImm();
       assert(isInt<12>(Offset));
 

llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll

@@ -1167,10 +1167,8 @@ declare void @f(ptr)
 define i32 @crash() {
 ; RV32I-LABEL: crash:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    lui a0, %hi(g)
-; RV32I-NEXT:    addi a0, a0, %lo(g)
-; RV32I-NEXT:    add a0, a0, zero
-; RV32I-NEXT:    lbu a0, 401(a0)
+; RV32I-NEXT:    lui a0, %hi(g+401)
+; RV32I-NEXT:    lbu a0, %lo(g+401)(a0)
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    sw a0, 0(zero)
 ; RV32I-NEXT:    li a0, 0
@@ -1179,21 +1177,17 @@ define i32 @crash() {
 ; RV32I-MEDIUM-LABEL: crash:
 ; RV32I-MEDIUM:       # %bb.0: # %entry
 ; RV32I-MEDIUM-NEXT:  .Lpcrel_hi14:
-; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi14)
-; RV32I-MEDIUM-NEXT:    add a0, a0, zero
-; RV32I-MEDIUM-NEXT:    lbu a0, 401(a0)
+; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g+401)
+; RV32I-MEDIUM-NEXT:    lbu a0, %pcrel_lo(.Lpcrel_hi14)(a0)
 ; RV32I-MEDIUM-NEXT:    seqz a0, a0
 ; RV32I-MEDIUM-NEXT:    sw a0, 0(zero)
 ; RV32I-MEDIUM-NEXT:    li a0, 0
 ; RV32I-MEDIUM-NEXT:    ret
 ;
 ; RV64I-LABEL: crash:
 ; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    lui a0, %hi(g)
-; RV64I-NEXT:    addi a0, a0, %lo(g)
-; RV64I-NEXT:    add a0, a0, zero
-; RV64I-NEXT:    lbu a0, 401(a0)
+; RV64I-NEXT:    lui a0, %hi(g+401)
+; RV64I-NEXT:    lbu a0, %lo(g+401)(a0)
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    sw a0, 0(zero)
 ; RV64I-NEXT:    li a0, 0
@@ -1202,22 +1196,21 @@ define i32 @crash() {
 ; RV64I-MEDIUM-LABEL: crash:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:  .Lpcrel_hi14:
-; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g)
-; RV64I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi14)
-; RV64I-MEDIUM-NEXT:    add a0, a0, zero
-; RV64I-MEDIUM-NEXT:    lbu a0, 401(a0)
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(g+401)
+; RV64I-MEDIUM-NEXT:    lbu a0, %pcrel_lo(.Lpcrel_hi14)(a0)
 ; RV64I-MEDIUM-NEXT:    seqz a0, a0
 ; RV64I-MEDIUM-NEXT:    sw a0, 0(zero)
 ; RV64I-MEDIUM-NEXT:    li a0, 0
 ; RV64I-MEDIUM-NEXT:    ret
 ;
 ; RV64I-LARGE-LABEL: crash:
 ; RV64I-LARGE:       # %bb.0: # %entry
+; RV64I-LARGE-NEXT:    li a0, 1
 ; RV64I-LARGE-NEXT:  .Lpcrel_hi15:
-; RV64I-LARGE-NEXT:    auipc a0, %pcrel_hi(.LCPI21_0)
-; RV64I-LARGE-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi15)(a0)
-; RV64I-LARGE-NEXT:    add a0, a0, zero
-; RV64I-LARGE-NEXT:    lbu a0, 401(a0)
+; RV64I-LARGE-NEXT:    auipc a1, %pcrel_hi(.LCPI21_0)
+; RV64I-LARGE-NEXT:    ld a1, %pcrel_lo(.Lpcrel_hi15)(a1)
+; RV64I-LARGE-NEXT:    add a0, a1, a0
+; RV64I-LARGE-NEXT:    lbu a0, 400(a0)
 ; RV64I-LARGE-NEXT:    seqz a0, a0
 ; RV64I-LARGE-NEXT:    sw a0, 0(zero)
 ; RV64I-LARGE-NEXT:    li a0, 0