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add tests
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -passes=aggressive-instcombine < %s | FileCheck %s
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define i64 @narrow_add(i64 noundef %a, i64 noundef %b) {
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; CHECK-LABEL: define i64 @narrow_add(
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; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ZEXT0:%.*]] = and i64 [[A]], 2147483647
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; CHECK-NEXT: [[ZEXT1:%.*]] = and i64 [[B]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[ZEXT0]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[ZEXT1]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%zext0 = and i64 %a, 2147483647
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%zext1 = and i64 %b, 2147483647
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%add = add i64 %zext0, %zext1
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ret i64 %add
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}
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define i64 @narrow_mul(i64 noundef %a, i64 noundef %b) {
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; CHECK-LABEL: define i64 @narrow_mul(
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; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ZEXT0:%.*]] = and i64 [[A]], 2147483647
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; CHECK-NEXT: [[ZEXT1:%.*]] = and i64 [[B]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[ZEXT0]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[ZEXT1]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%zext0 = and i64 %a, 2147483647
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%zext1 = and i64 %b, 2147483647
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%mul = mul i64 %zext0, %zext1
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ret i64 %mul
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}
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define i64 @narrow_sub(i64 noundef %a, i64 noundef %b) {
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; CHECK-LABEL: define i64 @narrow_sub(
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; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ZEXT0:%.*]] = and i64 [[A]], 2147483647
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; CHECK-NEXT: [[ZEXT1:%.*]] = and i64 [[B]], 2147483647
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[ZEXT0]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[ZEXT1]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%zext0 = and i64 %a, 2147483647
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%zext1 = and i64 %b, 2147483647
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%sub = sub i64 %zext0, %zext1
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ret i64 %sub
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}
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define i64 @no_narrow_add(i64 noundef %a, i64 noundef %b) {
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; CHECK-LABEL: define i64 @no_narrow_add(
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; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ZEXT0:%.*]] = and i64 [[A]], 2147483648
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; CHECK-NEXT: [[ZEXT1:%.*]] = and i64 [[B]], 2147483648
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ZEXT0]], [[ZEXT1]]
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%zext0 = and i64 %a, 2147483648
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%zext1 = and i64 %b, 2147483648
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%add = add i64 %zext0, %zext1
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ret i64 %add
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}
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define i64 @no_narrow_mul(i64 noundef %a, i64 noundef %b) {
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; CHECK-LABEL: define i64 @no_narrow_mul(
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; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ZEXT0:%.*]] = and i64 [[A]], 2147483648
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; CHECK-NEXT: [[ZEXT1:%.*]] = and i64 [[B]], 2147483648
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[ZEXT0]], [[ZEXT1]]
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%zext0 = and i64 %a, 2147483648
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%zext1 = and i64 %b, 2147483648
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%mul = mul i64 %zext0, %zext1
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ret i64 %mul
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}
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define i64 @no_narrow_sub(i64 noundef %a, i64 noundef %b) {
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; CHECK-LABEL: define i64 @no_narrow_sub(
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; CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ZEXT0:%.*]] = and i64 [[A]], 2147483648
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; CHECK-NEXT: [[ZEXT1:%.*]] = and i64 [[B]], 2147483648
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; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[ZEXT0]], [[ZEXT1]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%zext0 = and i64 %a, 2147483648
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%zext1 = and i64 %b, 2147483648
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%sub = sub i64 %zext0, %zext1
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ret i64 %sub
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}

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