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--Updated the test file
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‎llvm/docs/SPIRVUsage.rst‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -243,6 +243,9 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
243243
- Adds execution mode and capability to enable maximal reconvergence.
244244
* - ``SPV_ALTERA_blocking_pipes``
245245
- Adds new pipe read and write functions that have blocking semantics instead of the non-blocking semantics of the existing pipe read/write functions.
246+
* - ``SPV_INTEL_arbitrary_precision_fixed_point``
247+
- Add instructions for fixed point arithmetic. The extension works without SPV_INTEL_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
248+
246249

247250
SPIR-V representation in LLVM IR
248251
================================

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2399,6 +2399,77 @@ static bool generateBlockingPipesInst(const SPIRV::IncomingCall *Call,
23992399
return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
24002400
}
24012401

2402+
static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
2403+
unsigned Opcode, MachineIRBuilder &MIRBuilder,
2404+
SPIRVGlobalRegistry *GR) {
2405+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2406+
SmallVector<uint32_t, 1> ImmArgs;
2407+
Register InputReg = Call->Arguments[0];
2408+
const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
2409+
bool IsSRet = RetTy->isVoidTy();
2410+
2411+
if (IsSRet) {
2412+
const LLT ValTy = MRI->getType(InputReg);
2413+
Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
2414+
SPIRVType *InstructionType =
2415+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2416+
InputReg = Call->Arguments[1];
2417+
auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
2418+
Register PtrInputReg;
2419+
if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
2420+
LLT InputLLT = MRI->getType(InputReg);
2421+
PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
2422+
SPIRVType *PtrType =
2423+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2424+
MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
2425+
MachinePointerInfo(), MachineMemOperand::MOLoad,
2426+
InputLLT.getSizeInBytes(), Align(4));
2427+
MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
2428+
MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
2429+
GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
2430+
}
2431+
2432+
for (unsigned index = 2; index < 7; index++) {
2433+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2434+
}
2435+
2436+
// Emit the instruction
2437+
auto MIB = MIRBuilder.buildInstr(Opcode)
2438+
.addDef(ActualRetValReg)
2439+
.addUse(GR->getSPIRVTypeID(InstructionType));
2440+
if (PtrInputReg)
2441+
MIB.addUse(PtrInputReg);
2442+
else
2443+
MIB.addUse(InputReg);
2444+
2445+
for (uint32_t Imm : ImmArgs)
2446+
MIB.addImm(Imm);
2447+
unsigned Size = ValTy.getSizeInBytes();
2448+
// Store result to the pointer passed in Arg[0]
2449+
MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
2450+
MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
2451+
MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
2452+
MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
2453+
return true;
2454+
} else {
2455+
for (unsigned index = 1; index < 6; index++)
2456+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2457+
2458+
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
2459+
GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
2460+
}
2461+
}
2462+
2463+
static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
2464+
MachineIRBuilder &MIRBuilder,
2465+
SPIRVGlobalRegistry *GR) {
2466+
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
2467+
unsigned Opcode =
2468+
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
2469+
2470+
return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
2471+
}
2472+
24022473
static bool
24032474
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
24042475
MachineIRBuilder &MIRBuilder,
@@ -3051,6 +3122,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
30513122
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
30523123
case SPIRV::BindlessINTEL:
30533124
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
3125+
case SPIRV::ArbitraryPrecisionFixedPoint:
3126+
return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
30543127
case SPIRV::TernaryBitwiseINTEL:
30553128
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
30563129
case SPIRV::Block2DLoadStore:

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ def TernaryBitwiseINTEL : BuiltinGroup;
7171
def Block2DLoadStore : BuiltinGroup;
7272
def Pipe : BuiltinGroup;
7373
def PredicatedLoadStore : BuiltinGroup;
74+
def ArbitraryPrecisionFixedPoint : BuiltinGroup;
7475
def BlockingPipes : BuiltinGroup;
7576

7677
//===----------------------------------------------------------------------===//
@@ -1181,6 +1182,19 @@ defm : DemangledNativeBuiltin<"__spirv_WritePipeBlockingINTEL", OpenCL_std, Bloc
11811182
defm : DemangledNativeBuiltin<"__spirv_ReadPipeBlockingINTEL", OpenCL_std, BlockingPipes, 0, 0, OpReadPipeBlockingALTERA>;
11821183
defm : DemangledNativeBuiltin<"__spirv_ReadClockKHR", OpenCL_std, KernelClock, 1, 1, OpReadClockKHR>;
11831184

1185+
//SPV_INTEL_arbitrary_precision_fixed_point
1186+
defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
1187+
defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
1188+
defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
1189+
defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
1190+
defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
1191+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
1192+
defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
1193+
defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
1194+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
1195+
defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
1196+
defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
1197+
11841198
//===----------------------------------------------------------------------===//
11851199
// Class defining an atomic instruction on floating-point numbers.
11861200
//

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,11 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
161161
{"SPV_INTEL_kernel_attributes",
162162
SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes},
163163
{"SPV_ALTERA_blocking_pipes",
164-
SPIRV::Extension::Extension::SPV_ALTERA_blocking_pipes}};
164+
SPIRV::Extension::Extension::SPV_ALTERA_blocking_pipes},
165+
{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
166+
{"SPV_ALTERA_arbitrary_precision_fixed_point",
167+
SPIRV::Extension::Extension::
168+
SPV_ALTERA_arbitrary_precision_fixed_point}};
165169

166170
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
167171
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 24 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -994,8 +994,27 @@ def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr,
994994
def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
995995
"OpPredicatedStoreINTEL $ptr $object $predicate">;
996996

997-
//SPV_ALTERA_blocking_pipes
998-
def OpReadPipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
999-
"OpReadPipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;
1000-
def OpWritePipeBlockingALTERA :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
1001-
"OpWritePipeBlockingALTERA $pipe $pointer $packetSize $packetAlignment">;
997+
//SPV_INTEL_arbitrary_precision_fixed_point
998+
def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
999+
"$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
1000+
def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1001+
"$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
1002+
def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1003+
"$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
1004+
def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1005+
"$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
1006+
def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1007+
"$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
1008+
def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1009+
"$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
1010+
def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1011+
"$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
1012+
def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1013+
"$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
1014+
def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1015+
"$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
1016+
def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1017+
"$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
1018+
def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1019+
"$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
1020+

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1670,6 +1670,27 @@ void addInstrRequirements(const MachineInstr &MI,
16701670
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
16711671
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
16721672
break;
1673+
case SPIRV::OpFixedCosINTEL:
1674+
case SPIRV::OpFixedSinINTEL:
1675+
case SPIRV::OpFixedCosPiINTEL:
1676+
case SPIRV::OpFixedSinPiINTEL:
1677+
case SPIRV::OpFixedExpINTEL:
1678+
case SPIRV::OpFixedLogINTEL:
1679+
case SPIRV::OpFixedRecipINTEL:
1680+
case SPIRV::OpFixedSqrtINTEL:
1681+
case SPIRV::OpFixedSinCosINTEL:
1682+
case SPIRV::OpFixedSinCosPiINTEL:
1683+
case SPIRV::OpFixedRsqrtINTEL:
1684+
if (!ST.canUseExtension(
1685+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
1686+
report_fatal_error("This instruction requires the "
1687+
"following SPIR-V extension: "
1688+
"SPV_INTEL_arbitrary_precision_fixed_point",
1689+
false);
1690+
Reqs.addExtension(
1691+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
1692+
Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
1693+
break;
16731694
case SPIRV::OpGroupIMulKHR:
16741695
case SPIRV::OpGroupFMulKHR:
16751696
case SPIRV::OpGroupBitwiseAndKHR:

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -389,6 +389,7 @@ defm SPV_INTEL_predicated_io : ExtensionOperand<127, [EnvOpenCL]>;
389389
defm SPV_KHR_maximal_reconvergence : ExtensionOperand<128, [EnvVulkan]>;
390390
defm SPV_INTEL_bfloat16_arithmetic
391391
: ExtensionOperand<129, [EnvVulkan, EnvOpenCL]>;
392+
defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<130, [EnvOpenCL]>;
392393

393394
//===----------------------------------------------------------------------===//
394395
// Multiclass used to define Capabilities enum values and at the same time
@@ -608,10 +609,12 @@ defm PredicatedIOINTEL : CapabilityOperand<6257, 0, 0, [SPV_INTEL_predicated_io]
608609
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
609610
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
610611
defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>;
612+
<<<<<<< HEAD
611613
defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>;
612614
defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>;
613615
defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
614616
defm BlockingPipesALTERA : CapabilityOperand<5945, 0, 0, [SPV_ALTERA_blocking_pipes], []>;
617+
defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
615618

616619
//===----------------------------------------------------------------------===//
617620
// Multiclass used to define SourceLanguage enum values and at the same time

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