Reorder model includes in RISCV.td

ppenzin · ppenzin · commit 10b416c01b5a · 2024-12-16T18:04:48.000-06:00
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -53,8 +53,8 @@ include "RISCVSchedSiFiveP600.td"
 include "RISCVSchedSyntacoreSCR1.td"
 include "RISCVSchedSyntacoreSCR345.td"
 include "RISCVSchedSyntacoreSCR7.td"
-include "RISCVSchedXiangShanNanHu.td"
 include "RISCVSchedTTAscalonD8.td"
+include "RISCVSchedXiangShanNanHu.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
