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Fix asserts
Change-Id: I2131d6510e74dc1a7c58ebe8007455cb3540a0f3
1 parent 7e501d5 commit 10d53b0

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llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1627,10 +1627,14 @@ bool PreRARematStage::allUsesAvailableAt(const MachineInstr *InstToRemat,
16271627
if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
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continue;
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1630-
// Do not attempt to reason about PhysRegs
16311630
if (!MO.getReg().isVirtual()) {
1632-
assert(DAG.MRI.isConstantPhysReg(MO.getReg()) ||
1633-
DAG.TII->isIgnorableUse(MO));
1631+
// Do not attempt to reason about PhysRegs
1632+
// TODO: better analysis of PhysReg livness
1633+
if (!DAG.MRI.isConstantPhysReg(MO.getReg()) &&
1634+
!DAG.TII->isIgnorableUse(MO))
1635+
return false;
1636+
1637+
// Constant PhysRegs and IgnorableUses are okay
16341638
continue;
16351639
}
16361640

@@ -1664,7 +1668,6 @@ bool PreRARematStage::allUsesAvailableAt(const MachineInstr *InstToRemat,
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if (LM.none())
16651669
break;
16661670
}
1667-
assert(LM.none());
16681671
}
16691672
}
16701673
return true;
@@ -1856,10 +1859,7 @@ bool PreRARematStage::sinkTriviallyRematInsts(const GCNSubtarget &ST,
18561859
MachineBasicBlock::iterator InsertPos =
18571860
MachineBasicBlock::iterator(It.second);
18581861
Register Reg = Def->getOperand(0).getReg();
1859-
// Rematerialize MI to its use block. Since we are only rematerializing
1860-
// instructions that do not have any virtual reg uses, we do not need to
1861-
// call LiveRangeEdit::allUsesAvailableAt() and
1862-
// LiveRangeEdit::canRematerializeAt().
1862+
// Rematerialize MI to its use block.
18631863
TII->reMaterialize(*InsertPos->getParent(), InsertPos, Reg,
18641864
Def->getOperand(0).getSubReg(), *Def, *DAG.TRI);
18651865
MachineInstr *NewMI = &*std::prev(InsertPos);

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