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Thorsten Schütt
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[GlobalISel][AArch64] Legalize G_EXTRACT_SUBVECTOR (#112946)
for future combines
1 parent 093d4db commit 10f6d01

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4 files changed

+124
-47
lines changed

4 files changed

+124
-47
lines changed

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,7 @@ def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>;
147147
def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;
148148
def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
149149
def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
150+
def : GINodeEquiv<G_EXTRACT_SUBVECTOR, extract_subvector>;
150151
def : GINodeEquiv<G_FCEIL, fceil>;
151152
def : GINodeEquiv<G_FCOS, fcos>;
152153
def : GINodeEquiv<G_FSIN, fsin>;

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1282,6 +1282,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
12821282

12831283
getActionDefinitionsBuilder({G_SCMP, G_UCMP}).lower();
12841284

1285+
getActionDefinitionsBuilder(G_EXTRACT_SUBVECTOR)
1286+
.legalFor({{v8s8, v16s8}, {v4s16, v8s16}, {v2s32, v4s32}})
1287+
.widenScalarOrEltToNextPow2(0)
1288+
.immIdx(0); // Inform verifier imm idx 0 is handled.
1289+
12851290
getLegacyLegalizerInfo().computeTables();
12861291
verify(*ST.getInstrInfo());
12871292
}

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -652,8 +652,8 @@
652652
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
653653
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
654654
# DEBUG-NEXT: G_EXTRACT_SUBVECTOR (opcode {{[0-9]+}}): 2 type indices, 1 imm index
655-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
656-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
655+
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
656+
# DEBUG-NEXT: .. the first uncovered imm index: 1, OK
657657
# DEBUG-NEXT: G_INSERT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices
658658
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
659659
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected

‎llvm/test/CodeGen/AArch64/extract-subvec-combine.ll‎

Lines changed: 116 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1,62 +1,100 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK
2+
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
define <2 x i32> @and_extract_zext_idx0(<4 x i16> %vec) nounwind {
5-
; CHECK-LABEL: and_extract_zext_idx0:
6-
; CHECK: // %bb.0:
7-
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
8-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
9-
; CHECK-NEXT: ret
6+
; CHECK-SD-LABEL: and_extract_zext_idx0:
7+
; CHECK-SD: // %bb.0:
8+
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
9+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
10+
; CHECK-SD-NEXT: ret
11+
;
12+
; CHECK-GI-LABEL: and_extract_zext_idx0:
13+
; CHECK-GI: // %bb.0:
14+
; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff
15+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
16+
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
17+
; CHECK-GI-NEXT: ret
1018
%zext = zext <4 x i16> %vec to <4 x i32>
1119
%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
1220
%and = and <2 x i32> %extract, <i32 65535, i32 65535>
1321
ret <2 x i32> %and
1422
}
1523

1624
define <4 x i16> @and_extract_sext_idx0(<8 x i8> %vec) nounwind {
17-
; CHECK-LABEL: and_extract_sext_idx0:
18-
; CHECK: // %bb.0:
19-
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
20-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
21-
; CHECK-NEXT: ret
25+
; CHECK-SD-LABEL: and_extract_sext_idx0:
26+
; CHECK-SD: // %bb.0:
27+
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
28+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
29+
; CHECK-SD-NEXT: ret
30+
;
31+
; CHECK-GI-LABEL: and_extract_sext_idx0:
32+
; CHECK-GI: // %bb.0:
33+
; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
34+
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
35+
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
36+
; CHECK-GI-NEXT: ret
2237
%sext = sext <8 x i8> %vec to <8 x i16>
2338
%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)
2439
%and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
2540
ret <4 x i16> %and
2641
}
2742

2843
define <2 x i32> @and_extract_zext_idx2(<4 x i16> %vec) nounwind {
29-
; CHECK-LABEL: and_extract_zext_idx2:
30-
; CHECK: // %bb.0:
31-
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
32-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
33-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
34-
; CHECK-NEXT: ret
44+
; CHECK-SD-LABEL: and_extract_zext_idx2:
45+
; CHECK-SD: // %bb.0:
46+
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
47+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
48+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
49+
; CHECK-SD-NEXT: ret
50+
;
51+
; CHECK-GI-LABEL: and_extract_zext_idx2:
52+
; CHECK-GI: // %bb.0:
53+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
54+
; CHECK-GI-NEXT: movi d1, #0x00ffff0000ffff
55+
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
56+
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
57+
; CHECK-GI-NEXT: ret
3558
%zext = zext <4 x i16> %vec to <4 x i32>
3659
%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)
3760
%and = and <2 x i32> %extract, <i32 65535, i32 65535>
3861
ret <2 x i32> %and
3962
}
4063

4164
define <4 x i16> @and_extract_sext_idx4(<8 x i8> %vec) nounwind {
42-
; CHECK-LABEL: and_extract_sext_idx4:
43-
; CHECK: // %bb.0:
44-
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
45-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
46-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
47-
; CHECK-NEXT: ret
65+
; CHECK-SD-LABEL: and_extract_sext_idx4:
66+
; CHECK-SD: // %bb.0:
67+
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
68+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
69+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
70+
; CHECK-SD-NEXT: ret
71+
;
72+
; CHECK-GI-LABEL: and_extract_sext_idx4:
73+
; CHECK-GI: // %bb.0:
74+
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
75+
; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
76+
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
77+
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
78+
; CHECK-GI-NEXT: ret
4879
%sext = sext <8 x i8> %vec to <8 x i16>
4980
%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)
5081
%and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
5182
ret <4 x i16> %and
5283
}
5384

5485
define <2 x i32> @sext_extract_zext_idx0(<4 x i16> %vec) nounwind {
55-
; CHECK-LABEL: sext_extract_zext_idx0:
56-
; CHECK: // %bb.0:
57-
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
58-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
59-
; CHECK-NEXT: ret
86+
; CHECK-SD-LABEL: sext_extract_zext_idx0:
87+
; CHECK-SD: // %bb.0:
88+
; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
89+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
90+
; CHECK-SD-NEXT: ret
91+
;
92+
; CHECK-GI-LABEL: sext_extract_zext_idx0:
93+
; CHECK-GI: // %bb.0:
94+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
95+
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
96+
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
97+
; CHECK-GI-NEXT: ret
6098
%zext = zext <4 x i16> %vec to <4 x i32>
6199
%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
62100
%sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>
@@ -80,11 +118,18 @@ define <2 x i32> @sext_extract_zext_idx0_negtest(<4 x i16> %vec) nounwind {
80118
}
81119

82120
define <4 x i16> @sext_extract_sext_idx0(<8 x i8> %vec) nounwind {
83-
; CHECK-LABEL: sext_extract_sext_idx0:
84-
; CHECK: // %bb.0:
85-
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
86-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
87-
; CHECK-NEXT: ret
121+
; CHECK-SD-LABEL: sext_extract_sext_idx0:
122+
; CHECK-SD: // %bb.0:
123+
; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
124+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
125+
; CHECK-SD-NEXT: ret
126+
;
127+
; CHECK-GI-LABEL: sext_extract_sext_idx0:
128+
; CHECK-GI: // %bb.0:
129+
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
130+
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8
131+
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8
132+
; CHECK-GI-NEXT: ret
88133
%sext = sext <8 x i8> %vec to <8 x i16>
89134
%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)
90135
%sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>
@@ -93,12 +138,20 @@ define <4 x i16> @sext_extract_sext_idx0(<8 x i8> %vec) nounwind {
93138
}
94139

95140
define <2 x i32> @sext_extract_zext_idx2(<4 x i16> %vec) nounwind {
96-
; CHECK-LABEL: sext_extract_zext_idx2:
97-
; CHECK: // %bb.0:
98-
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
99-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
100-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
101-
; CHECK-NEXT: ret
141+
; CHECK-SD-LABEL: sext_extract_zext_idx2:
142+
; CHECK-SD: // %bb.0:
143+
; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
144+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
145+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
146+
; CHECK-SD-NEXT: ret
147+
;
148+
; CHECK-GI-LABEL: sext_extract_zext_idx2:
149+
; CHECK-GI: // %bb.0:
150+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
151+
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
152+
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16
153+
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16
154+
; CHECK-GI-NEXT: ret
102155
%zext = zext <4 x i16> %vec to <4 x i32>
103156
%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)
104157
%sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>
@@ -107,18 +160,36 @@ define <2 x i32> @sext_extract_zext_idx2(<4 x i16> %vec) nounwind {
107160
}
108161

109162
define <4 x i16> @sext_extract_sext_idx4(<8 x i8> %vec) nounwind {
110-
; CHECK-LABEL: sext_extract_sext_idx4:
111-
; CHECK: // %bb.0:
112-
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
113-
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
114-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
115-
; CHECK-NEXT: ret
163+
; CHECK-SD-LABEL: sext_extract_sext_idx4:
164+
; CHECK-SD: // %bb.0:
165+
; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
166+
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
167+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
168+
; CHECK-SD-NEXT: ret
169+
;
170+
; CHECK-GI-LABEL: sext_extract_sext_idx4:
171+
; CHECK-GI: // %bb.0:
172+
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
173+
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
174+
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #8
175+
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #8
176+
; CHECK-GI-NEXT: ret
116177
%sext = sext <8 x i8> %vec to <8 x i16>
117178
%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)
118179
%sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>
119180
%sext_inreg = ashr <4 x i16> %sext_inreg_step0, <i16 8, i16 8, i16 8, i16 8>
120181
ret <4 x i16> %sext_inreg
121182
}
122183

184+
define <8 x i8> @sext_extract_idx(<16 x i8> %vec) nounwind {
185+
; CHECK-LABEL: sext_extract_idx:
186+
; CHECK: // %bb.0:
187+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
188+
; CHECK-NEXT: ret
189+
%extract = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %vec, i64 0)
190+
ret <8 x i8> %extract
191+
}
192+
123193
declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
124194
declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
195+
declare <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8>, i64)

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