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1 parent f2849fe commit 10f983aCopy full SHA for 10f983a
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -30,8 +30,6 @@ def VCIX_XVW : VCIXType<0b1111>;
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// The payload and tsimm5 operands are all marked as ImmArg in the IR
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// intrinsic and will be target constant, so use TImmLeaf rather than ImmLeaf.
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class PayloadOp<int bitsNum> : RISCVOp, TImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);"> {
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- let ParserMatchClass = UImmAsmOperand<bitsNum>;
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- let DecoderMethod = "decodeUImmOperand<"# bitsNum # ">";
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let OperandType = "OPERAND_UIMM" # bitsNum;
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}
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