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mahesh-attardemattarde
mahesh-attarde
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mattarde
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[AMX][NFC] Organize tilerow (#168193)
Organizing tilerow for an extension. --------- Co-authored-by: mattarde <[email protected]>
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‎llvm/lib/Target/X86/X86ExpandPseudo.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -608,40 +608,40 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
608608
Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDT1);
609609
break;
610610
case X86::PTCVTROWD2PSrreV:
611-
Opc = X86::TCVTROWD2PSrre;
611+
Opc = X86::TCVTROWD2PSrte;
612612
break;
613613
case X86::PTCVTROWD2PSrriV:
614-
Opc = X86::TCVTROWD2PSrri;
614+
Opc = X86::TCVTROWD2PSrti;
615615
break;
616616
case X86::PTCVTROWPS2BF16HrreV:
617-
Opc = X86::TCVTROWPS2BF16Hrre;
617+
Opc = X86::TCVTROWPS2BF16Hrte;
618618
break;
619619
case X86::PTCVTROWPS2BF16HrriV:
620-
Opc = X86::TCVTROWPS2BF16Hrri;
620+
Opc = X86::TCVTROWPS2BF16Hrti;
621621
break;
622622
case X86::PTCVTROWPS2BF16LrreV:
623-
Opc = X86::TCVTROWPS2BF16Lrre;
623+
Opc = X86::TCVTROWPS2BF16Lrte;
624624
break;
625625
case X86::PTCVTROWPS2BF16LrriV:
626-
Opc = X86::TCVTROWPS2BF16Lrri;
626+
Opc = X86::TCVTROWPS2BF16Lrti;
627627
break;
628628
case X86::PTCVTROWPS2PHHrreV:
629-
Opc = X86::TCVTROWPS2PHHrre;
629+
Opc = X86::TCVTROWPS2PHHrte;
630630
break;
631631
case X86::PTCVTROWPS2PHHrriV:
632-
Opc = X86::TCVTROWPS2PHHrri;
632+
Opc = X86::TCVTROWPS2PHHrti;
633633
break;
634634
case X86::PTCVTROWPS2PHLrreV:
635-
Opc = X86::TCVTROWPS2PHLrre;
635+
Opc = X86::TCVTROWPS2PHLrte;
636636
break;
637637
case X86::PTCVTROWPS2PHLrriV:
638-
Opc = X86::TCVTROWPS2PHLrri;
638+
Opc = X86::TCVTROWPS2PHLrti;
639639
break;
640640
case X86::PTILEMOVROWrreV:
641-
Opc = X86::TILEMOVROWrre;
641+
Opc = X86::TILEMOVROWrte;
642642
break;
643643
case X86::PTILEMOVROWrriV:
644-
Opc = X86::TILEMOVROWrri;
644+
Opc = X86::TILEMOVROWrti;
645645
break;
646646
default:
647647
llvm_unreachable("Unexpected Opcode");

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -38364,22 +38364,22 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3836438364
default:
3836538365
llvm_unreachable("Unexpected instruction!");
3836638366
case X86::PTCVTROWD2PSrri:
38367-
Opc = X86::TCVTROWD2PSrri;
38367+
Opc = X86::TCVTROWD2PSrti;
3836838368
break;
3836938369
case X86::PTCVTROWPS2BF16Hrri:
38370-
Opc = X86::TCVTROWPS2BF16Hrri;
38370+
Opc = X86::TCVTROWPS2BF16Hrti;
3837138371
break;
3837238372
case X86::PTCVTROWPS2PHHrri:
38373-
Opc = X86::TCVTROWPS2PHHrri;
38373+
Opc = X86::TCVTROWPS2PHHrti;
3837438374
break;
3837538375
case X86::PTCVTROWPS2BF16Lrri:
38376-
Opc = X86::TCVTROWPS2BF16Lrri;
38376+
Opc = X86::TCVTROWPS2BF16Lrti;
3837738377
break;
3837838378
case X86::PTCVTROWPS2PHLrri:
38379-
Opc = X86::TCVTROWPS2PHLrri;
38379+
Opc = X86::TCVTROWPS2PHLrti;
3838038380
break;
3838138381
case X86::PTILEMOVROWrri:
38382-
Opc = X86::TILEMOVROWrri;
38382+
Opc = X86::TILEMOVROWrti;
3838338383
break;
3838438384
}
3838538385
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
@@ -38402,22 +38402,22 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3840238402
default:
3840338403
llvm_unreachable("Unexpected instruction!");
3840438404
case X86::PTCVTROWD2PSrre:
38405-
Opc = X86::TCVTROWD2PSrre;
38405+
Opc = X86::TCVTROWD2PSrte;
3840638406
break;
3840738407
case X86::PTCVTROWPS2BF16Hrre:
38408-
Opc = X86::TCVTROWPS2BF16Hrre;
38408+
Opc = X86::TCVTROWPS2BF16Hrte;
3840938409
break;
3841038410
case X86::PTCVTROWPS2BF16Lrre:
38411-
Opc = X86::TCVTROWPS2BF16Lrre;
38411+
Opc = X86::TCVTROWPS2BF16Lrte;
3841238412
break;
3841338413
case X86::PTCVTROWPS2PHHrre:
38414-
Opc = X86::TCVTROWPS2PHHrre;
38414+
Opc = X86::TCVTROWPS2PHHrte;
3841538415
break;
3841638416
case X86::PTCVTROWPS2PHLrre:
38417-
Opc = X86::TCVTROWPS2PHLrre;
38417+
Opc = X86::TCVTROWPS2PHLrte;
3841838418
break;
3841938419
case X86::PTILEMOVROWrre:
38420-
Opc = X86::TILEMOVROWrre;
38420+
Opc = X86::TILEMOVROWrte;
3842138421
break;
3842238422
}
3842338423
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));

‎llvm/lib/Target/X86/X86InstrAMX.td‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -370,11 +370,11 @@ let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {
370370
multiclass m_tcvtrowd2ps {
371371
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
372372
let SchedRW = [WriteSystem] in {
373-
def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
373+
def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
374374
(ins TILE:$src1, i32u8imm:$src2),
375375
"tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
376376
[]>, TA,XS, EVEX, EVEX_V512;
377-
def rre : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
377+
def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
378378
(ins TILE:$src1, GR32:$src2),
379379
"tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
380380
[]>, T8,XS, EVEX, VVVV, EVEX_V512;
@@ -450,12 +450,12 @@ multiclass AMXAVX512_BASE<bits<8> Opcode1, bits<8> Opcode2, string Opstr,
450450
Prefix P1, Prefix P2> {
451451
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode], SchedRW = [WriteSystem] in {
452452
let OpPrefix = P1 in
453-
def rre : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),
453+
def rte : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),
454454
(ins TILE:$src1, GR32:$src2),
455455
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
456456
[]>, EVEX, VVVV, EVEX_V512, T8;
457457
let OpPrefix = P2 in
458-
def rri : Ii8<Opcode2, MRMSrcReg, (outs VR512:$dst),
458+
def rti : Ii8<Opcode2, MRMSrcReg, (outs VR512:$dst),
459459
(ins TILE:$src1, i32u8imm:$src2),
460460
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
461461
[]>, EVEX, EVEX_V512, TA;
@@ -475,22 +475,22 @@ defm TCVTROWPS2PHL : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2phl", PD, XD>;
475475
defm TCVTROWPS2BF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2bf16h", XD, XD>;
476476
defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;
477477

478-
multiclass m_tilemovrow {
478+
multiclass AMXAVX512_TILEMOVE<bits<8> Opcode1, bits<8> Opcode2, string Opstr> {
479479
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
480480
let SchedRW = [WriteSystem] in {
481-
def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
481+
def rti : Ii8<Opcode1, MRMSrcReg, (outs VR512:$dst),
482482
(ins TILE:$src1, u8imm:$src2),
483-
"tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}",
484-
[]>, TA,PD, EVEX, EVEX_V512;
485-
def rre : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
483+
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
484+
[]>, TA, PD, EVEX, EVEX_V512;
485+
def rte : I<Opcode2, MRMSrcReg4VOp3, (outs VR512:$dst),
486486
(ins TILE:$src1, GR32:$src2),
487-
"tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}",
488-
[]>, T8,PD, EVEX, VVVV, EVEX_V512;
487+
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
488+
[]>, T8, PD, EVEX, VVVV, EVEX_V512;
489489
}
490490
} // HasAMXAVX512, HasAVX10_2, In64BitMode
491491
}
492492

493-
defm TILEMOVROW : m_tilemovrow;
493+
defm TILEMOVROW : AMXAVX512_TILEMOVE<0x07, 0x4A, "tilemovrow">;
494494

495495
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
496496
let SchedRW = [WriteSystem] in {

‎llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1737,8 +1737,8 @@ Key: TILELOADDRST: [ 0.00 0.00 ]
17371737
Key: TILELOADDRS_EVEX: [ 0.00 0.00 ]
17381738
Key: TILELOADDT: [ 0.00 0.00 ]
17391739
Key: TILELOADD_EVEX: [ 0.00 0.00 ]
1740-
Key: TILEMOVROWrre: [ 0.00 0.00 ]
1741-
Key: TILEMOVROWrri: [ 0.00 0.00 ]
1740+
Key: TILEMOVROWrte: [ 0.00 0.00 ]
1741+
Key: TILEMOVROWrti: [ 0.00 0.00 ]
17421742
Key: TILERELEASE: [ 0.00 0.00 ]
17431743
Key: TILESTORED: [ 0.00 0.00 ]
17441744
Key: TILESTORED_EVEX: [ 0.00 0.00 ]

‎llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1737,8 +1737,8 @@ Key: TILELOADDRST: [ 0.00 0.00 ]
17371737
Key: TILELOADDRS_EVEX: [ 0.00 0.00 ]
17381738
Key: TILELOADDT: [ 0.00 0.00 ]
17391739
Key: TILELOADD_EVEX: [ 0.00 0.00 ]
1740-
Key: TILEMOVROWrre: [ 0.00 0.00 ]
1741-
Key: TILEMOVROWrri: [ 0.00 0.00 ]
1740+
Key: TILEMOVROWrte: [ 0.00 0.00 ]
1741+
Key: TILEMOVROWrti: [ 0.00 0.00 ]
17421742
Key: TILERELEASE: [ 0.00 0.00 ]
17431743
Key: TILESTORED: [ 0.00 0.00 ]
17441744
Key: TILESTORED_EVEX: [ 0.00 0.00 ]

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