Add tests

Author: rj-jesus

llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll

@@ -285,8 +285,8 @@ define void @nxv2f32(ptr %ldptr, ptr %stptr) {
 ; CHECK-2048-NEXT:    ret
   %ldoff = getelementptr inbounds nuw i8, ptr %ldptr, i64 64
   %stoff = getelementptr inbounds nuw i8, ptr %stptr, i64 64
-  %x = load <vscale x 2 x float>, ptr %ldoff, align 1
-  store <vscale x 2 x float> %x, ptr %stoff, align 1
+  %x = load <vscale x 2 x float>, ptr %ldoff, align 4
+  store <vscale x 2 x float> %x, ptr %stoff, align 4
   ret void
 }
 
@@ -356,7 +356,116 @@ define void @nxv4f64(ptr %ldptr, ptr %stptr) {
 ; CHECK-2048-NEXT:    ret
   %ldoff = getelementptr inbounds nuw i8, ptr %ldptr, i64 128
   %stoff = getelementptr inbounds nuw i8, ptr %stptr, i64 128
-  %x = load <vscale x 4 x double>, ptr %ldoff, align 1
-  store <vscale x 4 x double> %x, ptr %stoff, align 1
+  %x = load <vscale x 4 x double>, ptr %ldoff, align 8
+  store <vscale x 4 x double> %x, ptr %stoff, align 8
+  ret void
+}
+
+define void @v8i32(ptr %ldptr, ptr %stptr) {
+; CHECK-LABEL: v8i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldp q0, q1, [x0, #64]
+; CHECK-NEXT:    ldp q3, q2, [x0, #32]
+; CHECK-NEXT:    stp q0, q1, [x1, #64]
+; CHECK-NEXT:    stp q3, q2, [x1, #32]
+; CHECK-NEXT:    ret
+;
+; CHECK-128-LABEL: v8i32:
+; CHECK-128:       // %bb.0:
+; CHECK-128-NEXT:    ldp q0, q1, [x0, #64]
+; CHECK-128-NEXT:    ldp q3, q2, [x0, #32]
+; CHECK-128-NEXT:    stp q0, q1, [x1, #64]
+; CHECK-128-NEXT:    stp q3, q2, [x1, #32]
+; CHECK-128-NEXT:    ret
+;
+; CHECK-256-LABEL: v8i32:
+; CHECK-256:       // %bb.0:
+; CHECK-256-NEXT:    ptrue p0.s
+; CHECK-256-NEXT:    mov x8, #8 // =0x8
+; CHECK-256-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
+; CHECK-256-NEXT:    ld1w { z1.s }, p0/z, [x0, #1, mul vl]
+; CHECK-256-NEXT:    st1w { z0.s }, p0, [x1, x8, lsl #2]
+; CHECK-256-NEXT:    st1w { z1.s }, p0, [x1, #1, mul vl]
+; CHECK-256-NEXT:    ret
+;
+; CHECK-512-LABEL: v8i32:
+; CHECK-512:       // %bb.0:
+; CHECK-512-NEXT:    ptrue p0.s
+; CHECK-512-NEXT:    mov x8, #8 // =0x8
+; CHECK-512-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
+; CHECK-512-NEXT:    st1w { z0.s }, p0, [x1, x8, lsl #2]
+; CHECK-512-NEXT:    ret
+;
+; CHECK-1024-LABEL: v8i32:
+; CHECK-1024:       // %bb.0:
+; CHECK-1024-NEXT:    ptrue p0.s, vl16
+; CHECK-1024-NEXT:    mov x8, #8 // =0x8
+; CHECK-1024-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
+; CHECK-1024-NEXT:    st1w { z0.s }, p0, [x1, x8, lsl #2]
+; CHECK-1024-NEXT:    ret
+;
+; CHECK-2048-LABEL: v8i32:
+; CHECK-2048:       // %bb.0:
+; CHECK-2048-NEXT:    ptrue p0.s, vl16
+; CHECK-2048-NEXT:    mov x8, #8 // =0x8
+; CHECK-2048-NEXT:    ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
+; CHECK-2048-NEXT:    st1w { z0.s }, p0, [x1, x8, lsl #2]
+; CHECK-2048-NEXT:    ret
+  %ldoff = getelementptr inbounds nuw i8, ptr %ldptr, i64 32
+  %stoff = getelementptr inbounds nuw i8, ptr %stptr, i64 32
+  %x = load <16 x i32>, ptr %ldoff, align 4
+  store <16 x i32> %x, ptr %stoff, align 4
+  ret void
+}
+
+; FIXME: This is wrong for VLS.
+define void @v8i32_vscale(ptr %0) {
+; CHECK-LABEL: v8i32_vscale:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v0.4s, #1
+; CHECK-NEXT:    rdvl x8, #2
+; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    stp q0, q0, [x8]
+; CHECK-NEXT:    ret
+;
+; CHECK-128-LABEL: v8i32_vscale:
+; CHECK-128:       // %bb.0:
+; CHECK-128-NEXT:    movi v0.4s, #1
+; CHECK-128-NEXT:    rdvl x8, #2
+; CHECK-128-NEXT:    add x8, x0, x8
+; CHECK-128-NEXT:    stp q0, q0, [x8]
+; CHECK-128-NEXT:    ret
+;
+; CHECK-256-LABEL: v8i32_vscale:
+; CHECK-256:       // %bb.0:
+; CHECK-256-NEXT:    mov z0.s, #1 // =0x1
+; CHECK-256-NEXT:    ptrue p0.s
+; CHECK-256-NEXT:    st1w { z0.s }, p0, [x0, #1, mul vl]
+; CHECK-256-NEXT:    ret
+;
+; CHECK-512-LABEL: v8i32_vscale:
+; CHECK-512:       // %bb.0:
+; CHECK-512-NEXT:    mov z0.s, #1 // =0x1
+; CHECK-512-NEXT:    ptrue p0.s, vl8
+; CHECK-512-NEXT:    st1w { z0.s }, p0, [x0, #1, mul vl]
+; CHECK-512-NEXT:    ret
+;
+; CHECK-1024-LABEL: v8i32_vscale:
+; CHECK-1024:       // %bb.0:
+; CHECK-1024-NEXT:    mov z0.s, #1 // =0x1
+; CHECK-1024-NEXT:    ptrue p0.s, vl8
+; CHECK-1024-NEXT:    st1w { z0.s }, p0, [x0, #1, mul vl]
+; CHECK-1024-NEXT:    ret
+;
+; CHECK-2048-LABEL: v8i32_vscale:
+; CHECK-2048:       // %bb.0:
+; CHECK-2048-NEXT:    mov z0.s, #1 // =0x1
+; CHECK-2048-NEXT:    ptrue p0.s, vl8
+; CHECK-2048-NEXT:    st1w { z0.s }, p0, [x0, #1, mul vl]
+; CHECK-2048-NEXT:    ret
+  %vl = call i64 @llvm.vscale()
+  %vlx = shl i64 %vl, 5
+  %2 = getelementptr inbounds nuw i8, ptr %0, i64 %vlx
+  store <8 x i32> splat (i32 1), ptr %2, align 4
   ret void
 }