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[gn build] Manually port ed3597e
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8 files changed

+25
-6
lines changed

8 files changed

+25
-6
lines changed

llvm/utils/gn/secondary/llvm/lib/Target/AArch64/Disassembler/BUILD.gn

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,8 @@ tablegen("AArch64GenDisassemblerTables") {
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visibility = [ ":Disassembler" ]
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args = [
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"-gen-disassembler",
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"--large-decoder-table",
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"-ignore-non-decodable-operands",
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"-ignore-fully-defined-operands",
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]
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td_file = "../AArch64.td"
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}

llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@ tablegen("AMDGPUGenDisassemblerTables") {
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args = [
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"-gen-disassembler",
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"-specialize-decoders-per-bitwidth",
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"-ignore-non-decodable-operands",
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"-ignore-fully-defined-operands",
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]
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td_file = "../AMDGPU.td"
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}

llvm/utils/gn/secondary/llvm/lib/Target/ARM/Disassembler/BUILD.gn

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,10 @@ import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("ARMGenDisassemblerTables") {
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visibility = [ ":Disassembler" ]
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args = [ "-gen-disassembler" ]
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args = [
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"-gen-disassembler",
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"-ignore-non-decodable-operands",
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]
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td_file = "../ARM.td"
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}
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llvm/utils/gn/secondary/llvm/lib/Target/AVR/Disassembler/BUILD.gn

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,10 @@ import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("AVRGenDisassemblerTables") {
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visibility = [ ":Disassembler" ]
5-
args = [ "-gen-disassembler" ]
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args = [
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"-gen-disassembler",
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"-ignore-non-decodable-operands",
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]
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td_file = "../AVR.td"
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}
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llvm/utils/gn/secondary/llvm/lib/Target/BPF/Disassembler/BUILD.gn

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,10 @@ import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("BPFGenDisassemblerTables") {
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visibility = [ ":Disassembler" ]
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args = [ "-gen-disassembler" ]
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args = [
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"-gen-disassembler",
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"-ignore-non-decodable-operands",
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]
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td_file = "../BPF.td"
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}
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llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/Disassembler/BUILD.gn

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,10 @@ import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("HexagonGenDisassemblerTables") {
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visibility = [ ":Disassembler" ]
5-
args = [ "-gen-disassembler" ]
5+
args = [
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"-gen-disassembler",
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"-ignore-non-decodable-operands",
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]
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td_file = "../Hexagon.td"
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}
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llvm/utils/gn/secondary/llvm/lib/Target/Mips/Disassembler/BUILD.gn

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,10 @@ import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("MipsGenDisassemblerTables") {
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visibility = [ ":Disassembler" ]
5-
args = [ "-gen-disassembler" ]
5+
args = [
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"-gen-disassembler",
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"-ignore-non-decodable-operands",
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]
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td_file = "../Mips.td"
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}
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llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Disassembler/BUILD.gn

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ tablegen("RISCVGenDisassemblerTables") {
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args = [
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"-gen-disassembler",
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"-specialize-decoders-per-bitwidth",
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"-ignore-non-decodable-operands",
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]
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td_file = "../RISCV.td"
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}

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