@@ -7785,16 +7785,16 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan(
77857785
77867786 BestVPlan.execute (&State);
77877787
7788- auto *ExitVPBB = BestVPlan.getMiddleBlock ();
7788+ auto *MiddleVPBB = BestVPlan.getMiddleBlock ();
77897789 // 2.5 When vectorizing the epilogue, fix reduction and induction resume
77907790 // values from the additional bypass block.
77917791 if (VectorizingEpilogue) {
77927792 assert (!ILV.Legal ->hasUncountableEarlyExit () &&
77937793 " Epilogue vectorisation not yet supported with early exits" );
77947794 BasicBlock *BypassBlock = ILV.getAdditionalBypassBlock ();
7795- for (VPRecipeBase &R : *ExitVPBB ) {
7795+ for (VPRecipeBase &R : *MiddleVPBB ) {
77967796 fixReductionScalarResumeWhenVectorizingEpilog (
7797- &R, State, State.CFG .VPBB2IRBB [ExitVPBB ], BypassBlock);
7797+ &R, State, State.CFG .VPBB2IRBB [MiddleVPBB ], BypassBlock);
77987798 }
77997799 BasicBlock *PH = OrigLoop->getLoopPreheader ();
78007800 for (const auto &[IVPhi, _] : Legal->getInductionVars ()) {
@@ -7840,7 +7840,7 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan(
78407840
78417841 // 4. Adjust branch weight of the branch in the middle block.
78427842 auto *MiddleTerm =
7843- cast<BranchInst>(State.CFG .VPBB2IRBB [ExitVPBB ]->getTerminator ());
7843+ cast<BranchInst>(State.CFG .VPBB2IRBB [MiddleVPBB ]->getTerminator ());
78447844 if (MiddleTerm->isConditional () &&
78457845 hasBranchWeightMD (*OrigLoop->getLoopLatch ()->getTerminator ())) {
78467846 // Assume that `Count % VectorTripCount` is equally distributed.
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