fixup! [RISCV] GPR Pairs for Inline Asm using Pr

This commit is an alternate approach that follows SystemZ in using
MVT::Untyped for GPR Pairs rather than new MVTs.

This approach does not need to use getAsmOperandValueType, so I have
also undone the fixes for this in TargetLowering.cpp. I will open a
separate PR against AArch64 to land this fix.

Author: lenary

llvm/include/llvm/CodeGen/ValueTypes.td

@@ -317,23 +317,20 @@ def riscv_nxv16i8x3  : VTVecTup<384, 3, i8, 220>; // RISCV vector tuple(min_num_
 def riscv_nxv16i8x4  : VTVecTup<512, 4, i8, 221>; // RISCV vector tuple(min_num_elts=16, nf=4)
 def riscv_nxv32i8x2  : VTVecTup<512, 2, i8, 222>; // RISCV vector tuple(min_num_elts=32, nf=2)
 
-def riscv_i32_pair : ValueType<64, 223>; // RISCV pair of RV32 GPRs
-def riscv_i64_pair : ValueType<128, 224>; // RISCV pair of RV64 GPRs
-
-def x86mmx    : ValueType<64,   225>;  // X86 MMX value
-def Glue      : ValueType<0,    226>;  // Pre-RA sched glue
-def isVoid    : ValueType<0,    227>;  // Produces no value
-def untyped   : ValueType<8,    228> { // Produces an untyped value
+def x86mmx    : ValueType<64,   223>;  // X86 MMX value
+def Glue      : ValueType<0,    224>;  // Pre-RA sched glue
+def isVoid    : ValueType<0,    225>;  // Produces no value
+def untyped   : ValueType<8,    226> { // Produces an untyped value
   let LLVMName = "Untyped";
 }
-def funcref   : ValueType<0,    229>;  // WebAssembly's funcref type
-def externref : ValueType<0,    230>;  // WebAssembly's externref type
-def exnref    : ValueType<0,    231>;  // WebAssembly's exnref type
-def x86amx    : ValueType<8192, 232>;  // X86 AMX value
-def i64x8     : ValueType<512,  233>;  // 8 Consecutive GPRs (AArch64)
+def funcref   : ValueType<0,    227>;  // WebAssembly's funcref type
+def externref : ValueType<0,    228>;  // WebAssembly's externref type
+def exnref    : ValueType<0,    229>;  // WebAssembly's exnref type
+def x86amx    : ValueType<8192, 230>;  // X86 AMX value
+def i64x8     : ValueType<512,  231>;  // 8 Consecutive GPRs (AArch64)
 def aarch64svcount
-              : ValueType<16,  234>;  // AArch64 predicate-as-counter
-def spirvbuiltin : ValueType<0, 235>; // SPIR-V's builtin type
+              : ValueType<16,  232>;  // AArch64 predicate-as-counter
+def spirvbuiltin : ValueType<0, 233>; // SPIR-V's builtin type
 
 let isNormalValueType = false in {
 def token      : ValueType<0, 504>;  // TokenTy

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -5753,8 +5753,7 @@ TargetLowering::ParseConstraints(const DataLayout &DL,
       assert(!Call.getType()->isVoidTy() && "Bad inline asm!");
       if (auto *STy = dyn_cast<StructType>(Call.getType())) {
         OpInfo.ConstraintVT =
-            getAsmOperandValueType(DL, STy->getElementType(ResNo))
-                .getSimpleVT();
+            getSimpleValueType(DL, STy->getElementType(ResNo));
       } else {
         assert(ResNo == 0 && "Asm only has one result!");
         OpInfo.ConstraintVT =

llvm/lib/CodeGen/ValueTypes.cpp

@@ -177,10 +177,6 @@ std::string EVT::getEVTString() const {
     if (isFloatingPoint())
       return "f" + utostr(getSizeInBits());
     llvm_unreachable("Invalid EVT!");
-  case MVT::riscv_i32_pair:
-    return "riscv_i32_pair";
-  case MVT::riscv_i64_pair:
-    return "riscv_i64_pair";
   case MVT::bf16:      return "bf16";
   case MVT::ppcf128:   return "ppcf128";
   case MVT::isVoid:    return "isVoid";
@@ -218,8 +214,6 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
     assert(isExtended() && "Type is not extended!");
     return LLVMTy;
   case MVT::isVoid:  return Type::getVoidTy(Context);
-  case MVT::riscv_i32_pair: return IntegerType::get(Context, 64);
-  case MVT::riscv_i64_pair: return IntegerType::get(Context, 128);
   case MVT::x86mmx:  return llvm::FixedVectorType::get(llvm::IntegerType::get(Context, 64), 1);
   case MVT::aarch64svcount:
     return TargetExtType::get(Context, "aarch64.svcount");

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -961,7 +961,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
         CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)};
 
     SDNode *N = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
-                                       Subtarget->getXLenPairVT(), Ops);
+                                       MVT::Untyped, Ops);
     ReplaceNode(Node, N);
     return;
   }

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -113,11 +113,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   }
 
   MVT XLenVT = Subtarget.getXLenVT();
-  MVT XLenPairVT = Subtarget.getXLenPairVT();
 
   // Set up the register classes.
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
-  addRegisterClass(XLenPairVT, &RISCV::GPRPairRegClass);
 
   if (Subtarget.hasStdExtZfhmin())
     addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
@@ -297,11 +295,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setCondCodeAction(ISD::SETLE, XLenVT, Expand);
   }
 
-  if (Subtarget.is64Bit())
-    setOperationAction(ISD::BITCAST, MVT::i128, Custom);
-  else
-    setOperationAction(ISD::BITCAST, MVT::i64, Custom);
-
   setOperationAction({ISD::STACKSAVE, ISD::STACKRESTORE}, MVT::Other, Expand);
 
   setOperationAction(ISD::VASTART, MVT::Other, Custom);
@@ -2218,17 +2211,6 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
   return (ResElts * 2) == SrcElts && (Index == 0 || Index == ResElts);
 }
 
-EVT RISCVTargetLowering::getAsmOperandValueType(const DataLayout &DL, Type *Ty,
-                                                bool AllowUnknown) const {
-  if (!Subtarget.is64Bit() && Ty->isIntegerTy(64))
-    return MVT::riscv_i32_pair;
-
-  if (Subtarget.is64Bit() && Ty->isIntegerTy(128))
-    return MVT::riscv_i64_pair;
-
-  return TargetLowering::getAsmOperandValueType(DL, Ty, AllowUnknown);
-}
-
 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
                                                       CallingConv::ID CC,
                                                       EVT VT) const {
@@ -2248,7 +2230,7 @@ RISCVTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT,
                                      std::optional<MVT> RegisterVT) const {
   // Pair inline assembly operand
   if (VT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) && RegisterVT &&
-      *RegisterVT == Subtarget.getXLenPairVT())
+      *RegisterVT == MVT::Untyped)
     return 1;
 
   return TargetLowering::getNumRegisters(Context, VT, RegisterVT);
@@ -2794,19 +2776,6 @@ RISCVTargetLowering::computeVLMAXBounds(MVT VecVT,
   return std::make_pair(MinVLMAX, MaxVLMAX);
 }
 
-bool RISCVTargetLowering::isLoadBitCastBeneficial(
-    EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
-    const MachineMemOperand &MMO) const {
-  // We want to leave `bitcasts` to/from MVT::riscv_i<xlen>_pair separate from
-  // loads/stores so they can be turned into BuildGPRPair/::SplitGPRPair nodes.
-  if (LoadVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) &&
-      BitcastVT == Subtarget.getXLenPairVT())
-    return false;
-
-  return TargetLoweringBase::isLoadBitCastBeneficial(LoadVT, BitcastVT, DAG,
-                                                     MMO);
-}
-
 // The state of RVV BUILD_VECTOR and VECTOR_SHUFFLE lowering is that very few
 // of either is (currently) supported. This can get us into an infinite loop
 // where we try to lower a BUILD_VECTOR as a VECTOR_SHUFFLE as a BUILD_VECTOR
@@ -6470,13 +6439,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       std::tie(Lo, Hi) = DAG.SplitScalar(Op0, DL, MVT::i32, MVT::i32);
       return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
     }
-    if (VT == Subtarget.getXLenPairVT() && Op0VT.isScalarInteger() &&
-        Op0VT.getSizeInBits() == 2 * Subtarget.getXLen()) {
-      SDValue Lo, Hi;
-      std::tie(Lo, Hi) = DAG.SplitScalar(Op0, DL, XLenVT, XLenVT);
-      return DAG.getNode(RISCVISD::BuildGPRPair, DL, Subtarget.getXLenPairVT(),
-                         Lo, Hi);
-    }
 
     // Consider other scalar<->scalar casts as legal if the types are legal.
     // Otherwise expand them.
@@ -12999,14 +12961,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
                                    NewReg.getValue(0), NewReg.getValue(1));
       Results.push_back(RetReg);
-    } else if (VT.isInteger() &&
-               VT.getSizeInBits() == 2 * Subtarget.getXLen() &&
-               Op0VT == Subtarget.getXLenPairVT()) {
-      SDValue NewReg = DAG.getNode(RISCVISD::SplitGPRPair, DL,
-                                   DAG.getVTList(XLenVT, XLenVT), Op0);
-      SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, VT, NewReg.getValue(0),
-                                   NewReg.getValue(1));
-      Results.push_back(RetReg);
     } else if (!VT.isVector() && Op0VT.isFixedLengthVector() &&
                isTypeLegal(Op0VT)) {
       // Custom-legalize bitcasts from fixed-length vector types to illegal
@@ -21418,6 +21372,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
     unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
   bool IsABIRegCopy = CC.has_value();
   EVT ValueVT = Val.getValueType();
+
+  if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) &&
+      NumParts == 1 && PartVT == MVT::Untyped) {
+    // Pairs in Inline Assembly
+    MVT XLenVT = Subtarget.getXLenVT();
+    SDValue Lo, Hi;
+    std::tie(Lo, Hi) = DAG.SplitScalar(Val, DL, XLenVT, XLenVT);
+    Parts[0] = DAG.getNode(RISCVISD::BuildGPRPair, DL, MVT::Untyped, Lo, Hi);
+    return true;
+  }
+
   if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
       PartVT == MVT::f32) {
     // Cast the [b]f16 to i16, extend to i32, pad with ones to make a float
@@ -21489,6 +21454,17 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
     SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
     MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
   bool IsABIRegCopy = CC.has_value();
+
+  if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) &&
+      NumParts == 1 && PartVT == MVT::Untyped) {
+    // Pairs in Inline Assembly
+    MVT XLenVT = Subtarget.getXLenVT();
+    SDValue Res = DAG.getNode(RISCVISD::SplitGPRPair, DL,
+                              DAG.getVTList(XLenVT, XLenVT), Parts[0]);
+    return DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Res.getValue(0),
+                      Res.getValue(1));
+  }
+
   if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
       PartVT == MVT::f32) {
     SDValue Val = Parts[0];

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -554,9 +554,6 @@ class RISCVTargetLowering : public TargetLowering {
 
   bool softPromoteHalfType() const override { return true; }
 
-  EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty,
-                             bool AllowUnknown = false) const override;
-
   /// Return the register type for a given MVT, ensuring vectors are treated
   /// as a series of gpr sized integers.
   MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
@@ -602,10 +599,6 @@ class RISCVTargetLowering : public TargetLowering {
     return false;
   }
 
-  bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
-                               const SelectionDAG &DAG,
-                               const MachineMemOperand &MMO) const override;
-
   bool
   shouldExpandBuildVectorWithShuffles(EVT VT,
                                       unsigned DefinedValues) const override;

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

@@ -287,9 +287,7 @@ def GPRX1X5 :  GPRRegisterClass<(add X1, X5)>;
 //  Even-Odd GPR Pairs
 //===----------------------------------------------------------------------===//
 
-def XLenPairVT : ValueTypeByHwMode<
-      [RV32,           RV64],
-      [riscv_i32_pair, riscv_i64_pair]>;
+defvar XLenPairVT = untyped;
 
 def XLenPairRI : RegInfoByHwMode<
       [RV32,                RV64],

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -201,10 +201,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     return Min;
   }
 
-  MVT getXLenPairVT() const {
-    return is64Bit() ? MVT::riscv_i64_pair : MVT::riscv_i32_pair;
-  }
-
   /// If the ElementCount or TypeSize \p X is scalable and VScale (VLEN) is
   /// exactly known, returns \p X converted to a fixed quantity. Otherwise
   /// returns \p X unmodified.