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1 parent dd61ed6 commit 131c488Copy full SHA for 131c488
llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
@@ -63,8 +63,9 @@ define half @add_v3HalfH(<3 x half> %bin.rdx) {
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;
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; CHECK-SD-FP16-LABEL: add_v3HalfH:
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; CHECK-SD-FP16: // %bb.0:
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+; CHECK-SD-FP16-NEXT: movi d1, #0000000000000000
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; CHECK-SD-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-FP16-NEXT: mov v0.h[3], wzr
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+; CHECK-SD-FP16-NEXT: mov v0.h[3], v1.h[0]
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; CHECK-SD-FP16-NEXT: faddp v0.4h, v0.4h, v0.4h
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; CHECK-SD-FP16-NEXT: faddp h0, v0.2h
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; CHECK-SD-FP16-NEXT: ret
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