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quic-akaryakiquic-akaryaki
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[Hexagon] Lowering saturating subtraction (#158726)
Saturating arithmetic can be expressed by llvm.uadd/usub.sat generic intrinsics.
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‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp‎

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@@ -208,6 +208,8 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::SPLAT_VECTOR, T, Legal);
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setOperationAction(ISD::UADDSAT, T, Legal);
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setOperationAction(ISD::SADDSAT, T, Legal);
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setOperationAction(ISD::USUBSAT, T, Legal);
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setOperationAction(ISD::SSUBSAT, T, Legal);
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if (T != ByteV) {
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
@@ -302,6 +304,8 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::UADDSAT, T, Legal);
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setOperationAction(ISD::SADDSAT, T, Legal);
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setOperationAction(ISD::SUB, T, Legal);
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setOperationAction(ISD::USUBSAT, T, Legal);
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setOperationAction(ISD::SSUBSAT, T, Legal);
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setOperationAction(ISD::MUL, T, Custom);
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setOperationAction(ISD::MULHS, T, Custom);
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setOperationAction(ISD::MULHU, T, Custom);

‎llvm/lib/Target/Hexagon/HexagonPatternsHVX.td‎

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@@ -441,6 +441,21 @@ let Predicates = [UseHVX] in {
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def: OpR_RR_pat_sat<V6_vaddwsat_dv, saddsat, VecPI32, HWI32>;
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}
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let Predicates = [UseHVX] in {
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def: OpR_RR_pat_sat<V6_vsububsat, usubsat, VecI8, HVI8>;
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def: OpR_RR_pat_sat<V6_vsubuhsat, usubsat, VecI16, HVI16>;
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def: OpR_RR_pat_sat<V6_vsubuwsat, usubsat, VecI32, HVI32>;
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def: OpR_RR_pat_sat<V6_vsubbsat, ssubsat, VecI8, HVI8>;
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def: OpR_RR_pat_sat<V6_vsubhsat, ssubsat, VecI16, HVI16>;
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def: OpR_RR_pat_sat<V6_vsubwsat, ssubsat, VecI32, HVI32>;
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def: OpR_RR_pat_sat<V6_vsububsat_dv, usubsat, VecPI8, HWI8>;
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def: OpR_RR_pat_sat<V6_vsubuhsat_dv, usubsat, VecPI16, HWI16>;
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def: OpR_RR_pat_sat<V6_vsubuwsat_dv, usubsat, VecPI32, HWI32>;
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def: OpR_RR_pat_sat<V6_vsubbsat_dv, ssubsat, VecPI8, HWI8>;
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def: OpR_RR_pat_sat<V6_vsubhsat_dv, ssubsat, VecPI16, HWI16>;
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def: OpR_RR_pat_sat<V6_vsubwsat_dv, ssubsat, VecPI32, HWI32>;
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}
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// For now, we always deal with vector floating point in SF mode.
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class OpR_RR_pat_conv<InstHexagon MI, PatFrag Op, ValueType ResType,
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PatFrag RsPred, PatFrag RtPred = RsPred>

‎llvm/test/CodeGen/Hexagon/vsubsat.ll‎

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@@ -0,0 +1,99 @@
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; RUN: llc -march=hexagon -mattr=+hvxv73,+hvx-length128b < %s | FileCheck %s
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;; Saturating subtraction.
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; CHECK-LABEL: vsububsat
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; CHECK: v[[#]].ub = vsub(v[[#]].ub,v[[#]].ub):sat
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define dso_local <128 x i8> @vsububsat(<128 x i8> %x, <128 x i8> %y) {
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entry:
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%0 = tail call <128 x i8> @llvm.usub.sat.v128i8(<128 x i8> %x, <128 x i8> %y)
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ret <128 x i8> %0
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}
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; CHECK-LABEL: vsubuhsat
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; CHECK: v[[#]].uh = vsub(v[[#]].uh,v[[#]].uh):sat
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define dso_local <64 x i16> @vsubuhsat(<64 x i16> %x, <64 x i16> %y) {
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entry:
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%0 = tail call <64 x i16> @llvm.usub.sat.v64i16(<64 x i16> %x, <64 x i16> %y)
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ret <64 x i16> %0
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}
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; CHECK-LABEL: vsubuwsat
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; CHECK: v[[#]].uw = vsub(v[[#]].uw,v[[#]].uw):sat
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define dso_local <32 x i32> @vsubuwsat(<32 x i32> %x, <32 x i32> %y) {
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entry:
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%0 = tail call <32 x i32> @llvm.usub.sat.v32i32(<32 x i32> %x, <32 x i32> %y)
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ret <32 x i32> %0
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}
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; CHECK-LABEL: vsubbsat
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; CHECK: v[[#]].b = vsub(v[[#]].b,v[[#]].b):sat
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define dso_local <128 x i8> @vsubbsat(<128 x i8> %x, <128 x i8> %y) {
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entry:
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%0 = tail call <128 x i8> @llvm.ssub.sat.v128i8(<128 x i8> %x, <128 x i8> %y)
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ret <128 x i8> %0
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}
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; CHECK-LABEL: vsubhsat
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; CHECK: v[[#]].h = vsub(v[[#]].h,v[[#]].h):sat
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define dso_local <64 x i16> @vsubhsat(<64 x i16> %x, <64 x i16> %y) {
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entry:
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%0 = tail call <64 x i16> @llvm.ssub.sat.v64i16(<64 x i16> %x, <64 x i16> %y)
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ret <64 x i16> %0
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}
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; CHECK-LABEL: vsubwsat
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; CHECK: v[[#]].w = vsub(v[[#]].w,v[[#]].w):sat
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define dso_local <32 x i32> @vsubwsat(<32 x i32> %x, <32 x i32> %y) {
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entry:
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%0 = tail call <32 x i32> @llvm.ssub.sat.v32i32(<32 x i32> %x, <32 x i32> %y)
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ret <32 x i32> %0
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}
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; CHECK-LABEL: vsububsat_dv
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; CHECK: v[[#]]:[[#]].ub = vsub(v[[#]]:[[#]].ub,v[[#]]:[[#]].ub):sat
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define dso_local <256 x i8> @vsububsat_dv(<256 x i8> %x, <256 x i8> %y) {
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entry:
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%0 = tail call <256 x i8> @llvm.usub.sat.v256i8(<256 x i8> %x, <256 x i8> %y)
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ret <256 x i8> %0
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}
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; CHECK-LABEL: vsubuhsat_dv
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; CHECK: v[[#]]:[[#]].uh = vsub(v[[#]]:[[#]].uh,v[[#]]:[[#]].uh):sat
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define dso_local <128 x i16> @vsubuhsat_dv(<128 x i16> %x, <128 x i16> %y) {
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entry:
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%0 = tail call <128 x i16> @llvm.usub.sat.v128i16(<128 x i16> %x, <128 x i16> %y)
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ret <128 x i16> %0
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}
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; CHECK-LABEL: vsubuwsat_dv
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; CHECK: v[[#]]:[[#]].uw = vsub(v[[#]]:[[#]].uw,v[[#]]:[[#]].uw):sat
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define dso_local <64 x i32> @vsubuwsat_dv(<64 x i32> %x, <64 x i32> %y) {
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entry:
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%0 = tail call <64 x i32> @llvm.usub.sat.v64i32(<64 x i32> %x, <64 x i32> %y)
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ret <64 x i32> %0
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}
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; CHECK-LABEL: vsubbsat_dv
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; CHECK: v[[#]]:[[#]].b = vsub(v[[#]]:[[#]].b,v[[#]]:[[#]].b):sat
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define dso_local <256 x i8> @vsubbsat_dv(<256 x i8> %x, <256 x i8> %y) {
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entry:
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%0 = tail call <256 x i8> @llvm.ssub.sat.v256i8(<256 x i8> %x, <256 x i8> %y)
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ret <256 x i8> %0
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}
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; CHECK-LABEL: vsubhsat_dv
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; CHECK: v[[#]]:[[#]].h = vsub(v[[#]]:[[#]].h,v[[#]]:[[#]].h):sat
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define dso_local <128 x i16> @vsubhsat_dv(<128 x i16> %x, <128 x i16> %y) {
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entry:
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%0 = tail call <128 x i16> @llvm.ssub.sat.v128i16(<128 x i16> %x, <128 x i16> %y)
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ret <128 x i16> %0
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}
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; CHECK-LABEL: vsubwsat_dv
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; CHECK: v[[#]]:[[#]].w = vsub(v[[#]]:[[#]].w,v[[#]]:[[#]].w):sat
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define dso_local <64 x i32> @vsubwsat_dv(<64 x i32> %x, <64 x i32> %y) {
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entry:
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%0 = tail call <64 x i32> @llvm.ssub.sat.v64i32(<64 x i32> %x, <64 x i32> %y)
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ret <64 x i32> %0
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}

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