Fix comments.

Author: simonzgx

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -397,7 +397,7 @@ namespace {
 
     SDValue foldShiftToAvg(SDNode *N);
     // Fold `a bitwiseop (~b +/- c)` -> `a bitwiseop ~(b -/+ c)`
-    SDValue foldBitwiseOpWithNeg(SDNode *N);
+    SDValue foldBitwiseOpWithNeg(SDNode *N, const SDLoc &DL, EVT VT);
 
     SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
                                 SDValue RHS, SDValue True, SDValue False,
@@ -7532,7 +7532,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
 
   // Fold (and X, (add (not Y), Z)) -> (and X, (not (sub Y, Z)))
   // Fold (and X, (sub (not Y), Z)) -> (and X, (not (add Y, Z)))
-  if (SDValue Folded = foldBitwiseOpWithNeg(N))
+  if (SDValue Folded = foldBitwiseOpWithNeg(N, DL, VT))
     return Folded;
 
   // Fold (and (srl X, C), 1) -> (srl X, BW-1) for signbit extraction
@@ -8214,7 +8214,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
 
   // Fold (or X, (add (not Y), Z)) -> (or X, (not (sub Y, Z)))
   // Fold (or X, (sub (not Y), Z)) -> (or X, (not (add Y, Z)))
-  if (SDValue Folded = foldBitwiseOpWithNeg(N))
+  if (SDValue Folded = foldBitwiseOpWithNeg(N, DL, VT))
     return Folded;
 
   // fold (or x, 0) -> x
@@ -9870,7 +9870,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
   }
   // Fold (xor X, (add (not Y), Z)) -> (xor X, (not (sub Y, Z)))
   // Fold (xor X, (sub (not Y), Z)) -> (xor X, (not (add Y, Z)))
-  if (SDValue Folded = foldBitwiseOpWithNeg(N))
+  if (SDValue Folded = foldBitwiseOpWithNeg(N, DL, VT))
     return Folded;
 
   // Simplify: xor (op x...), (op y...)  -> (op (xor x, y))
@@ -11625,28 +11625,21 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N) {
   return DAG.getNode(FloorISD, SDLoc(N), N->getValueType(0), {A, B});
 }
 
-SDValue DAGCombiner::foldBitwiseOpWithNeg(SDNode *N) {
+SDValue DAGCombiner::foldBitwiseOpWithNeg(SDNode *N, const SDLoc &DL, EVT VT) {
   if (!TLI.hasAndNot(SDValue(N, 0)))
     return SDValue();
 
   unsigned Opc = N->getOpcode();
-  if (Opc != ISD::AND && Opc != ISD::OR && Opc != ISD::XOR)
-    return SDValue();
-
-  SDValue N1 = N->getOperand(1);
-  EVT VT = N1.getValueType();
-  SDLoc DL(N);
   SDValue X, Y, Z, NotY;
-
-  if (sd_match(N, m_c_BinOp(Opc, m_Value(X),
-                            m_Add(m_AllOf(m_Value(NotY), m_Not(m_Value(Y))),
-                                  m_Value(Z)))))
+  if (sd_match(N, m_BitwiseLogic(m_Value(X), m_Add(m_AllOf(m_Value(NotY),
+                                                           m_Not(m_Value(Y))),
+                                                   m_Value(Z)))))
     return DAG.getNode(Opc, DL, VT, X,
                        DAG.getNOT(DL, DAG.getNode(ISD::SUB, DL, VT, Y, Z), VT));
 
-  if (sd_match(N, m_c_BinOp(Opc, m_Value(X),
-                            m_Sub(m_AllOf(m_Value(NotY), m_Not(m_Value(Y))),
-                                  m_Value(Z)))) &&
+  if (sd_match(N, m_BitwiseLogic(m_Value(X), m_Sub(m_AllOf(m_Value(NotY),
+                                                           m_Not(m_Value(Y))),
+                                                   m_Value(Z)))) &&
       NotY->hasOneUse())
     return DAG.getNode(Opc, DL, VT, X,
                        DAG.getNOT(DL, DAG.getNode(ISD::ADD, DL, VT, Y, Z), VT));

llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll

@@ -885,8 +885,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 define i8 @test_not_cttz_i8(i8 %a) nounwind {
 ; LA32R-LABEL: test_not_cttz_i8:
 ; LA32R:       # %bb.0:
-; LA32R-NEXT:    addi.w	$a1, $a0, 1
-; LA32R-NEXT:    andn	$a0, $a0, $a1
+; LA32R-NEXT:    addi.w $a1, $a0, 1
+; LA32R-NEXT:    andn $a0, $a0, $a1
 ; LA32R-NEXT:    srli.w $a1, $a0, 1
 ; LA32R-NEXT:    andi $a1, $a1, 85
 ; LA32R-NEXT:    sub.w $a0, $a0, $a1
@@ -920,8 +920,8 @@ define i8 @test_not_cttz_i8(i8 %a) nounwind {
 define i16 @test_not_cttz_i16(i16 %a) nounwind {
 ; LA32R-LABEL: test_not_cttz_i16:
 ; LA32R:       # %bb.0:
-; LA32R-NEXT:    addi.w	$a1, $a0, 1
-; LA32R-NEXT:    andn	$a0, $a0, $a1
+; LA32R-NEXT:    addi.w $a1, $a0, 1
+; LA32R-NEXT:    andn $a0, $a0, $a1
 ; LA32R-NEXT:    srli.w $a1, $a0, 1
 ; LA32R-NEXT:    lu12i.w $a2, 5
 ; LA32R-NEXT:    ori $a2, $a2, 1365