[test] Remove redundant -march= when target triple is specified in IR

MaskRay · MaskRay · commit 133352feb306 · 2024-12-15T12:42:17.000-08:00
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll b/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
@@ -1,4 +1,4 @@
-; clang -target aarch64-eabi -O2 -march=armv8.5-a+memtag -fsanitize=memtag -S -emit-llvm test.cc
+; clang -target aarch64-eabi -O2 -fsanitize=memtag -S -emit-llvm test.cc
 ; void bar() {
 ;   throw 42;
 ; }
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll b/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 
 ; Check that the cost model makes vectorization non-profitable.
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
 ; Check that the loop has been interleaved.
 ; CHECK: store <64 x i32> %interleaved.vec
 
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll b/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
 ; Check that the loop is vectorized with VF=32.
 ; CHECK: wide.load{{.*}} = load <32 x i32>
 ; CHECK: wide.load{{.*}} = load <32 x i16>
diff --git a/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll b/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -O2 -S < %s
+; RUN: opt -O2 -S < %s
 ; REQUIRES: asserts
 ;
 ; -fvectorize-loops infinite compile/memory
diff --git a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
@@ -1,4 +1,4 @@
-; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
+; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -mcpu=hexagonv60 -relocation-model pic
 
 ; CHECK: jumpr
 
diff --git a/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll b/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
@@ -1,4 +1,4 @@
-; RUN: opt -Os -march=hexagon -S < %s | FileCheck %s
+; RUN: opt -Os -S < %s | FileCheck %s
 ; Don't reset the alignment on the struct to 1.
 ; CHECK: align 4
 
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
 ; CHECK-LABEL: define void @fred
 
 ; Check that this test does not crash.
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
 ;
 ; The number of nested selects caused the simplification loop to take
 ; more than the maximum number of iterations. This caused the compiler
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
@@ -2,8 +2,8 @@
 ; the Hexagon loop idiom recognition runs. This is to check that we still
 ; get this opportunity regardless of what happens before.
 
-; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s
-; RUN: opt -passes='default<O2>' -march=hexagon -S < %s | FileCheck %s
+; RUN: opt -O2 -S < %s | FileCheck %s
+; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
 
 target triple = "hexagon"
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
 ; REQUIRES: asserts
 ;
 ; Check for sane output, this used to crash.
diff --git a/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll b/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-vc -S < %s | FileCheck %s
+; RUN: opt -hexagon-vc -S < %s | FileCheck %s
 
 ; Test that the HexagonVectorCombine pass identifies instruction
 ; pairs whose difference in pointers is zero. This creates a vector
diff --git a/llvm/test/CodeGen/Lanai/delay_filler.ll b/llvm/test/CodeGen/Lanai/delay_filler.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
-; RUN: llc -march=lanai --lanai-nop-delay-filler < %s | \
+; RUN: llc < %s | FileCheck %s
+; RUN: llc --lanai-nop-delay-filler < %s | \
 ; RUN:   FileCheck %s --check-prefix=NOP
 
 ; CHECK: bt f
diff --git a/llvm/test/CodeGen/Lanai/lowering-128.ll b/llvm/test/CodeGen/Lanai/lowering-128.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
+; RUN: llc < %s | FileCheck %s
 
 ; Tests that lowering wide registers (128 bits or more) works on Lanai.
 ; The emitted assembly is not checked, we just do a smoketest.
diff --git a/llvm/test/CodeGen/NVPTX/surf-read.ll b/llvm/test/CodeGen/NVPTX/surf-read.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
 
-target triple = "nvptx-unknown-nvcl"
+target triple = "nvptx64-unknown-nvcl"
 
 declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32)
 
diff --git a/llvm/test/CodeGen/NVPTX/surf-write.ll b/llvm/test/CodeGen/NVPTX/surf-write.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
 
 target triple = "nvptx-unknown-nvcl"
 
diff --git a/llvm/test/CodeGen/NVPTX/tex-read.ll b/llvm/test/CodeGen/NVPTX/tex-read.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
 
-target triple = "nvptx-unknown-nvcl"
+target triple = "nvptx64-unknown-nvcl"
 
 declare { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64, i64, i32)
 
diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
@@ -8,7 +8,7 @@
 ; Currently VSX support is disabled for this test because we generate lxsdx
 ; instead of lfd, and stxsdx instead of stfd.  That is a poor choice when we
 ; have reg+imm addressing, and is on the list of things to be fixed.
-; The second run step is to ensure that -march=ppc64le is adequate to select
+; The second run step is to ensure that is adequate to select
 ; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
 
 target datalayout = "e-m:e-i64:64-n32:64"
diff --git a/llvm/test/CodeGen/Thumb2/bug-subw.ll b/llvm/test/CodeGen/Thumb2/bug-subw.ll
@@ -1,5 +1,5 @@
 ; pr23772 - [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80"
-; RUN: llc -march=thumb -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
+; RUN: llc -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
 ; CHECK-NOT: sub{{.*}} sp, r{{.*}}, #
 ; CHECK:     .fnend
 ; TODO: Missed optimization. The three instructions generated to subtract SP can be converged to a single one
diff --git a/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll b/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_60 | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_60 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_60 | %ptxas-verify %}
 target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"
 
diff --git a/llvm/test/DebugInfo/X86/instr-ref-flag.ll b/llvm/test/DebugInfo/X86/instr-ref-flag.ll
@@ -1,10 +1,10 @@
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
 ; RUN: | FileCheck %s --check-prefixes=INSTRREFON
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
 ; RUN:    -experimental-debug-variable-locations=true \
 ; RUN: | FileCheck %s --check-prefixes=INSTRREFON
 
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
 ; RUN:    -experimental-debug-variable-locations=false \
 ; RUN: | FileCheck %s --check-prefixes=INSTRREFOFF \
 ; RUN:    --implicit-check-not=DBG_INSTR_REF
diff --git a/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll b/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
@@ -1,10 +1,10 @@
-; RUN: llc -O0  -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -O0  -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -force-instr-ref-livedebugvalues=1 -O0  -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -force-instr-ref-livedebugvalues=1 -O0  -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
 ; RUN:  | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
 
 ; The call-site-params are created iff corresponding DISubprogram contains
diff --git a/llvm/test/DebugInfo/X86/single-dbg_value.ll b/llvm/test/DebugInfo/X86/single-dbg_value.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -stop-after=livedebugvalues -o - %s \
 ; RUN:   | FileCheck %s --check-prefix=SANITY
-; RUN: llc -march=x86-64 -o - %s -filetype=obj \
+; RUN: llc -o - %s -filetype=obj \
 ; RUN:   | llvm-dwarfdump -v -all - | FileCheck %s
 ;
 ; CHECK: .debug_info contents:
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=load-store-vectorizer -march=nvptx64 -mcpu=sm_35 -S < %s | FileCheck %s
+; RUN: opt -passes=load-store-vectorizer -mcpu=sm_35 -S < %s | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"
diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
 ; RUN: opt < %s -passes=separate-const-offset-from-gep,slsr,gvn -S | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
+; RUN: llc < %s -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
 
 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
 target triple = "nvptx64-unknown-unknown"
diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
+; RUN: llc < %s -mcpu=sm_35 | FileCheck %s
 
 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; clang -target aarch64-eabi -O2 -march=armv8.5-a+memtag -fsanitize=memtag -S -emit-llvm test.cc`
	`1`	`+; clang -target aarch64-eabi -O2 -fsanitize=memtag -S -emit-llvm test.cc`
`2`	`2`	`; void bar() {`
`3`	`3`	`; throw 42;`
`4`	`4`	`; }`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: opt -march=hexagon -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 \| FileCheck %s`
	`1`	`+; RUN: opt -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 \| FileCheck %s`
`2`	`2`	`; REQUIRES: asserts`
`3`	`3`
`4`	`4`	`; Check that the cost model makes vectorization non-profitable.`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s \| FileCheck %s`
	`1`	`+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s \| FileCheck %s`
`2`	`2`	`; Check that the loop has been interleaved.`
`3`	`3`	`; CHECK: store <64 x i32> %interleaved.vec`
`4`	`4`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: opt -march=hexagon -O2 -S < %s`
	`1`	`+; RUN: opt -O2 -S < %s`
`2`	`2`	`; REQUIRES: asserts`
`3`	`3`	`;`
`4`	`4`	`; -fvectorize-loops infinite compile/memory`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s \| llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic`
	`1`	`+; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s \| llc -mcpu=hexagonv60 -relocation-model pic`
`2`	`2`
`3`	`3`	`; CHECK: jumpr`
`4`	`4`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: opt -Os -march=hexagon -S < %s \| FileCheck %s`
	`1`	`+; RUN: opt -Os -S < %s \| FileCheck %s`
`2`	`2`	`; Don't reset the alignment on the struct to 1.`
`3`	`3`	`; CHECK: align 4`
`4`	`4`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`		`-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s \| FileCheck %s`
`2`		`-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s \| FileCheck %s`
	`1`	`+; RUN: opt -hexagon-loop-idiom -S < %s \| FileCheck %s`
	`2`	`+; RUN: opt -p hexagon-loop-idiom -S < %s \| FileCheck %s`
`3`	`3`	`;`
`4`	`4`	`; The number of nested selects caused the simplification loop to take`
`5`	`5`	`; more than the maximum number of iterations. This caused the compiler`