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| 1 | +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 |
| 2 | +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -emit-llvm -o - | FileCheck %s |
| 3 | + |
| 4 | +using v1i = int [[clang::ext_vector_type(1)]]; |
| 5 | +using v1b = bool [[clang::ext_vector_type(1)]]; |
| 6 | +using v8i = int [[clang::ext_vector_type(8)]]; |
| 7 | +using v8b = bool [[clang::ext_vector_type(8)]]; |
| 8 | +using v16i = short [[clang::ext_vector_type(16)]]; |
| 9 | +using v16b = bool [[clang::ext_vector_type(16)]]; |
| 10 | +using v32i = char [[clang::ext_vector_type(32)]]; |
| 11 | +using v32b = bool [[clang::ext_vector_type(32)]]; |
| 12 | + |
| 13 | +// CHECK-LABEL: define dso_local noundef i8 @_Z3fooDv1_i( |
| 14 | +// CHECK-SAME: i32 noundef [[V_COERCE:%.*]]) #[[ATTR0:[0-9]+]] { |
| 15 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 16 | +// CHECK-NEXT: [[RETVAL:%.*]] = alloca <1 x i1>, align 1 |
| 17 | +// CHECK-NEXT: [[V:%.*]] = alloca <1 x i32>, align 4 |
| 18 | +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <1 x i32>, align 4 |
| 19 | +// CHECK-NEXT: store i32 [[V_COERCE]], ptr [[V]], align 4 |
| 20 | +// CHECK-NEXT: [[V1:%.*]] = load <1 x i32>, ptr [[V]], align 4 |
| 21 | +// CHECK-NEXT: store <1 x i32> [[V1]], ptr [[V_ADDR]], align 4 |
| 22 | +// CHECK-NEXT: [[TMP0:%.*]] = load <1 x i32>, ptr [[V_ADDR]], align 4 |
| 23 | +// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <1 x i32> [[TMP0]], zeroinitializer |
| 24 | +// CHECK-NEXT: store <1 x i1> [[TOBOOL]], ptr [[RETVAL]], align 1 |
| 25 | +// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[RETVAL]], align 1 |
| 26 | +// CHECK-NEXT: ret i8 [[TMP1]] |
| 27 | +// |
| 28 | +v1b foo(v1i v) { return v; } |
| 29 | +// CHECK-LABEL: define dso_local noundef i8 @_Z3fooDv8_i( |
| 30 | +// CHECK-SAME: ptr noundef byval(<8 x i32>) align 32 [[TMP0:%.*]]) #[[ATTR0]] { |
| 31 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 32 | +// CHECK-NEXT: [[RETVAL:%.*]] = alloca <8 x i1>, align 1 |
| 33 | +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <8 x i32>, align 32 |
| 34 | +// CHECK-NEXT: [[V:%.*]] = load <8 x i32>, ptr [[TMP0]], align 32 |
| 35 | +// CHECK-NEXT: store <8 x i32> [[V]], ptr [[V_ADDR]], align 32 |
| 36 | +// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[V_ADDR]], align 32 |
| 37 | +// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer |
| 38 | +// CHECK-NEXT: store <8 x i1> [[TOBOOL]], ptr [[RETVAL]], align 1 |
| 39 | +// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[RETVAL]], align 1 |
| 40 | +// CHECK-NEXT: ret i8 [[TMP2]] |
| 41 | +// |
| 42 | +v8b foo(v8i v) { return v; } |
| 43 | +// CHECK-LABEL: define dso_local noundef i16 @_Z3fooDv16_s( |
| 44 | +// CHECK-SAME: ptr noundef byval(<16 x i16>) align 32 [[TMP0:%.*]]) #[[ATTR0]] { |
| 45 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 46 | +// CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i1>, align 2 |
| 47 | +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <16 x i16>, align 32 |
| 48 | +// CHECK-NEXT: [[V:%.*]] = load <16 x i16>, ptr [[TMP0]], align 32 |
| 49 | +// CHECK-NEXT: store <16 x i16> [[V]], ptr [[V_ADDR]], align 32 |
| 50 | +// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr [[V_ADDR]], align 32 |
| 51 | +// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <16 x i16> [[TMP1]], zeroinitializer |
| 52 | +// CHECK-NEXT: store <16 x i1> [[TOBOOL]], ptr [[RETVAL]], align 2 |
| 53 | +// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[RETVAL]], align 2 |
| 54 | +// CHECK-NEXT: ret i16 [[TMP2]] |
| 55 | +// |
| 56 | +v16b foo(v16i v) { return v; } |
| 57 | +// CHECK-LABEL: define dso_local noundef i32 @_Z3fooDv32_c( |
| 58 | +// CHECK-SAME: ptr noundef byval(<32 x i8>) align 32 [[TMP0:%.*]]) #[[ATTR0]] { |
| 59 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 60 | +// CHECK-NEXT: [[RETVAL:%.*]] = alloca <32 x i1>, align 4 |
| 61 | +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <32 x i8>, align 32 |
| 62 | +// CHECK-NEXT: [[V:%.*]] = load <32 x i8>, ptr [[TMP0]], align 32 |
| 63 | +// CHECK-NEXT: store <32 x i8> [[V]], ptr [[V_ADDR]], align 32 |
| 64 | +// CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr [[V_ADDR]], align 32 |
| 65 | +// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <32 x i8> [[TMP1]], zeroinitializer |
| 66 | +// CHECK-NEXT: store <32 x i1> [[TOBOOL]], ptr [[RETVAL]], align 4 |
| 67 | +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| 68 | +// CHECK-NEXT: ret i32 [[TMP2]] |
| 69 | +// |
| 70 | +v32b foo(v32i v) { return v; } |
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