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[Reland][PatternMatch] Add m_[Shift]OrSelf matchers. NFC. (#154375)
Address the comment https://github.com/llvm/llvm-project/pull/147414/files#r2228612726. As they are usually used to match integer packing patterns, it is enough to handle constant shamts. Relands #152924. This patch removes the non-NFC changes in AggressiveInstCombine.
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llvm/include/llvm/IR/PatternMatch.h

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1328,6 +1328,45 @@ inline BinaryOp_match<LHS, RHS, Instruction::AShr> m_AShr(const LHS &L,
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return BinaryOp_match<LHS, RHS, Instruction::AShr>(L, R);
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}
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template <typename LHS_t, unsigned Opcode> struct ShiftLike_match {
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LHS_t L;
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uint64_t &R;
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ShiftLike_match(const LHS_t &LHS, uint64_t &RHS) : L(LHS), R(RHS) {}
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template <typename OpTy> bool match(OpTy *V) const {
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if (auto *Op = dyn_cast<BinaryOperator>(V)) {
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if (Op->getOpcode() == Opcode)
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return m_ConstantInt(R).match(Op->getOperand(1)) &&
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L.match(Op->getOperand(0));
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}
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// Interpreted as shiftop V, 0
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R = 0;
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return L.match(V);
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}
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};
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/// Matches shl L, ConstShAmt or L itself (R will be set to zero in this case).
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template <typename LHS>
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inline ShiftLike_match<LHS, Instruction::Shl> m_ShlOrSelf(const LHS &L,
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uint64_t &R) {
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return ShiftLike_match<LHS, Instruction::Shl>(L, R);
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}
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/// Matches lshr L, ConstShAmt or L itself (R will be set to zero in this case).
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template <typename LHS>
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inline ShiftLike_match<LHS, Instruction::LShr> m_LShrOrSelf(const LHS &L,
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uint64_t &R) {
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return ShiftLike_match<LHS, Instruction::LShr>(L, R);
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}
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/// Matches ashr L, ConstShAmt or L itself (R will be set to zero in this case).
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template <typename LHS>
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inline ShiftLike_match<LHS, Instruction::AShr> m_AShrOrSelf(const LHS &L,
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uint64_t &R) {
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return ShiftLike_match<LHS, Instruction::AShr>(L, R);
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}
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template <typename LHS_t, typename RHS_t, unsigned Opcode,
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unsigned WrapFlags = 0, bool Commutable = false>
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struct OverflowingBinaryOp_match {

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3640,16 +3640,11 @@ static bool matchSubIntegerPackFromVector(Value *V, Value *&Vec,
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int64_t &VecOffset,
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SmallBitVector &Mask,
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const DataLayout &DL) {
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static const auto m_ConstShlOrSelf = [](const auto &Base, uint64_t &ShlAmt) {
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ShlAmt = 0;
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return m_CombineOr(m_Shl(Base, m_ConstantInt(ShlAmt)), Base);
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};
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// First try to match extractelement -> zext -> shl
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uint64_t VecIdx, ShlAmt;
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if (match(V, m_ConstShlOrSelf(m_ZExtOrSelf(m_ExtractElt(
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m_Value(Vec), m_ConstantInt(VecIdx))),
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ShlAmt))) {
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if (match(V, m_ShlOrSelf(m_ZExtOrSelf(m_ExtractElt(m_Value(Vec),
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m_ConstantInt(VecIdx))),
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ShlAmt))) {
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auto *VecTy = dyn_cast<FixedVectorType>(Vec->getType());
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if (!VecTy)
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return false;

llvm/unittests/IR/PatternMatch.cpp

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2621,4 +2621,40 @@ TEST_F(PatternMatchTest, PtrAdd) {
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EXPECT_FALSE(match(OtherGEP, m_PtrAdd(m_Value(A), m_Value(B))));
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}
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TEST_F(PatternMatchTest, ShiftOrSelf) {
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Type *I64Ty = Type::getInt64Ty(Ctx);
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Constant *LHS = ConstantInt::get(I64Ty, 7);
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Constant *ShAmt = ConstantInt::get(I64Ty, 16);
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Value *Shl = IRB.CreateShl(LHS, ShAmt);
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Value *LShr = IRB.CreateLShr(LHS, ShAmt);
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Value *AShr = IRB.CreateAShr(LHS, ShAmt);
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Value *Add = IRB.CreateAdd(LHS, LHS);
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uint64_t ShAmtC;
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Value *A;
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EXPECT_TRUE(match(Shl, m_ShlOrSelf(m_Value(A), ShAmtC)));
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EXPECT_EQ(A, LHS);
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EXPECT_EQ(ShAmtC, 16U);
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EXPECT_TRUE(match(Add, m_ShlOrSelf(m_Value(A), ShAmtC)));
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EXPECT_EQ(A, Add);
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EXPECT_EQ(ShAmtC, 0U);
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EXPECT_TRUE(match(LShr, m_LShrOrSelf(m_Value(A), ShAmtC)));
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EXPECT_EQ(A, LHS);
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EXPECT_EQ(ShAmtC, 16U);
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2647+
EXPECT_TRUE(match(Add, m_LShrOrSelf(m_Value(A), ShAmtC)));
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EXPECT_EQ(A, Add);
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EXPECT_EQ(ShAmtC, 0U);
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EXPECT_TRUE(match(AShr, m_AShrOrSelf(m_Value(A), ShAmtC)));
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EXPECT_EQ(A, LHS);
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EXPECT_EQ(ShAmtC, 16U);
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EXPECT_TRUE(match(Add, m_AShrOrSelf(m_Value(A), ShAmtC)));
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EXPECT_EQ(A, Add);
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EXPECT_EQ(ShAmtC, 0U);
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}
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} // anonymous namespace.

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