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1 parent 15f87bc commit 13539c2Copy full SHA for 13539c2
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -188,8 +188,6 @@ class binop_with_non_imm12<SDPatternOperator binop>
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let PredicateCodeUsesOperands = 1;
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let GISelPredicateCode = [{
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const MachineOperand &ImmOp = *Operands[1];
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- const MachineFunction &MF = *MI.getParent()->getParent();
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- const MachineRegisterInfo &MRI = MF.getRegInfo();
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if (ImmOp.isReg() && ImmOp.getReg())
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if (auto Val = getIConstantVRegValWithLookThrough(ImmOp.getReg(), MRI)) {
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