Skip to content

Commit 1371e44

Browse files
djtodorodjtodoro
committed
fixup: address remaining comments
1 parent 751fecc commit 1371e44

File tree

4 files changed

+48
-252
lines changed

4 files changed

+48
-252
lines changed

‎llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ using namespace llvm;
3434
#define DEBUG_TYPE "riscv-load-store-opt"
3535
#define RISCV_LOAD_STORE_OPT_NAME "RISC-V Load / Store Optimizer"
3636

37-
// The LdStLimit limits number of basic blocks how far we search for load/store
37+
// The LdStLimit limits number of instructions how far we search for load/store
3838
// pairs.
3939
static cl::opt<unsigned> LdStLimit("riscv-load-store-scan-limit", cl::init(128),
4040
cl::Hidden);
@@ -82,7 +82,6 @@ struct RISCVLoadStoreOpt : public MachineFunctionPass {
8282
const RISCVInstrInfo *TII;
8383
const RISCVRegisterInfo *TRI;
8484
LiveRegUnits ModifiedRegUnits, UsedRegUnits;
85-
bool EnableLoadStorePairs = false;
8685
};
8786
} // end anonymous namespace
8887

@@ -94,8 +93,7 @@ bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
9493
if (skipFunction(Fn.getFunction()))
9594
return false;
9695
const RISCVSubtarget &Subtarget = Fn.getSubtarget<RISCVSubtarget>();
97-
EnableLoadStorePairs = Subtarget.useLoadStorePairs();
98-
if (!EnableLoadStorePairs)
96+
if (!Subtarget.useLoadStorePairs())
9997
return false;
10098

10199
bool MadeChange = false;
@@ -330,6 +328,10 @@ RISCVLoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
330328
bool MergeForward) {
331329
MachineBasicBlock::iterator E = I->getParent()->end();
332330
MachineBasicBlock::iterator NextI = next_nodbg(I, E);
331+
// If NextI is the second of the two instructions to be merged, we need
332+
// to skip one further. Either way we merge will invalidate the iterator,
333+
// and we don't need to scan the new instruction, as it's a pairwise
334+
// instruction, which we're not considering for further action anyway.
333335
if (NextI == Paired)
334336
NextI = next_nodbg(NextI, E);
335337

@@ -370,7 +372,7 @@ RISCVLoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
370372
First = InsertionPoint;
371373
}
372374

373-
if (EnableLoadStorePairs && tryConvertToLdStPair(First, Second)) {
375+
if (tryConvertToLdStPair(First, Second)) {
374376
LLVM_DEBUG(dbgs() << "Pairing load/store:\n ");
375377
LLVM_DEBUG(prev_nodbg(NextI, MBB.begin())->print(dbgs()));
376378
}

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -63,11 +63,11 @@ static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
6363
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
6464

6565
static cl::opt<bool> UseMIPSLoadStorePairsOpt(
66-
"riscv-mips-load-store-pairs",
66+
"use-riscv-mips-load-store-pairs",
6767
cl::desc("Enable the load/store pair optimization pass"), cl::init(false),
6868
cl::Hidden);
6969

70-
static cl::opt<bool> UseCCMovInsn("riscv-ccmov",
70+
static cl::opt<bool> UseCCMovInsn("use-riscv-ccmov",
7171
cl::desc("Use 'mips.ccmov' instruction"),
7272
cl::init(true), cl::Hidden);
7373

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -311,12 +311,7 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
311311
ScheduleDAGInstrs *
312312
RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
313313
ScheduleDAGMI *DAG = nullptr;
314-
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
315-
bool EnableLoadStoreClusteringForLoadStoreOpt =
316-
!ST.getMacroFusions().empty() && ST.useLoadStorePairs();
317-
318-
if (EnablePostMISchedLoadStoreClustering ||
319-
EnableLoadStoreClusteringForLoadStoreOpt) {
314+
if (EnablePostMISchedLoadStoreClustering) {
320315
DAG = createGenericSchedPostRA(C);
321316
DAG->addMutation(createLoadClusterDAGMutation(
322317
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));

‎llvm/test/CodeGen/RISCV/load-store-pair.ll‎

Lines changed: 38 additions & 239 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,24 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; testd and testf look for bonding only.
32
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
43
; RUN: | FileCheck %s -check-prefix=RV32I
5-
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+d -verify-machineinstrs < %s \
4+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+d -verify-machineinstrs < %s \
65
; RUN: | FileCheck %s -check-prefix=RV32D
76
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
87
; RUN: | FileCheck %s -check-prefix=RV64I
9-
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+d -verify-machineinstrs < %s \
8+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+d -verify-machineinstrs < %s \
109
; RUN: | FileCheck %s -check-prefix=RV64D
11-
; RUN: llc -mtriple=riscv32 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
10+
; RUN: llc -mtriple=riscv32 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1211
; RUN: | FileCheck %s -check-prefix=RV32I_PAIR
13-
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+d,+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
12+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+d,+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1413
; RUN: | FileCheck %s -check-prefix=RV32D_PAIR
15-
; RUN: llc -mtriple=riscv64 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
14+
; RUN: llc -mtriple=riscv64 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1615
; RUN: | FileCheck %s -check-prefix=RV64I_PAIR
17-
; RUN: llc -mtriple=riscv64 -mcpu mips-p8700 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
16+
; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1817
; RUN: | FileCheck %s -check-prefix=RV64P_8700
19-
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+d,+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
18+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+d,+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
2019
; RUN: | FileCheck %s -check-prefix=RV64D_PAIR
21-
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+d -verify-machineinstrs < %s \
22-
; RUN: | FileCheck %s -check-prefix=RV64D_8700
20+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+d -verify-machineinstrs < %s \
21+
; RUN: | FileCheck %s -check-prefix=RV64D_NOPAIR
2322

2423
define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_addr #0 {
2524
; RV32I-LABEL: testi:
@@ -268,35 +267,35 @@ define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_a
268267
; RV64D_PAIR-NEXT: .cfi_def_cfa_offset 0
269268
; RV64D_PAIR-NEXT: ret
270269
;
271-
; RV64D_8700-LABEL: testi:
272-
; RV64D_8700: # %bb.0: # %entry
273-
; RV64D_8700-NEXT: addi sp, sp, -32
274-
; RV64D_8700-NEXT: .cfi_def_cfa_offset 32
275-
; RV64D_8700-NEXT: sd s2, 24(sp) # 8-byte Folded Spill
276-
; RV64D_8700-NEXT: sd s3, 16(sp) # 8-byte Folded Spill
277-
; RV64D_8700-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
278-
; RV64D_8700-NEXT: sd s5, 0(sp) # 8-byte Folded Spill
279-
; RV64D_8700-NEXT: .cfi_offset s2, -8
280-
; RV64D_8700-NEXT: .cfi_offset s3, -16
281-
; RV64D_8700-NEXT: .cfi_offset s4, -24
282-
; RV64D_8700-NEXT: .cfi_offset s5, -32
283-
; RV64D_8700-NEXT: ld s3, 0(a0)
284-
; RV64D_8700-NEXT: ld s2, 8(a0)
285-
; RV64D_8700-NEXT: ld s5, 16(a0)
286-
; RV64D_8700-NEXT: ld s4, 24(a0)
287-
; RV64D_8700-NEXT: #APP
288-
; RV64D_8700-NEXT: #NO_APP
289-
; RV64D_8700-NEXT: ld s2, 24(sp) # 8-byte Folded Reload
290-
; RV64D_8700-NEXT: ld s3, 16(sp) # 8-byte Folded Reload
291-
; RV64D_8700-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
292-
; RV64D_8700-NEXT: ld s5, 0(sp) # 8-byte Folded Reload
293-
; RV64D_8700-NEXT: .cfi_restore s2
294-
; RV64D_8700-NEXT: .cfi_restore s3
295-
; RV64D_8700-NEXT: .cfi_restore s4
296-
; RV64D_8700-NEXT: .cfi_restore s5
297-
; RV64D_8700-NEXT: addi sp, sp, 32
298-
; RV64D_8700-NEXT: .cfi_def_cfa_offset 0
299-
; RV64D_8700-NEXT: ret
270+
; RV64D_NOPAIR-LABEL: testi:
271+
; RV64D_NOPAIR: # %bb.0: # %entry
272+
; RV64D_NOPAIR-NEXT: addi sp, sp, -32
273+
; RV64D_NOPAIR-NEXT: .cfi_def_cfa_offset 32
274+
; RV64D_NOPAIR-NEXT: sd s2, 24(sp) # 8-byte Folded Spill
275+
; RV64D_NOPAIR-NEXT: sd s3, 16(sp) # 8-byte Folded Spill
276+
; RV64D_NOPAIR-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
277+
; RV64D_NOPAIR-NEXT: sd s5, 0(sp) # 8-byte Folded Spill
278+
; RV64D_NOPAIR-NEXT: .cfi_offset s2, -8
279+
; RV64D_NOPAIR-NEXT: .cfi_offset s3, -16
280+
; RV64D_NOPAIR-NEXT: .cfi_offset s4, -24
281+
; RV64D_NOPAIR-NEXT: .cfi_offset s5, -32
282+
; RV64D_NOPAIR-NEXT: ld s3, 0(a0)
283+
; RV64D_NOPAIR-NEXT: ld s2, 8(a0)
284+
; RV64D_NOPAIR-NEXT: ld s5, 16(a0)
285+
; RV64D_NOPAIR-NEXT: ld s4, 24(a0)
286+
; RV64D_NOPAIR-NEXT: #APP
287+
; RV64D_NOPAIR-NEXT: #NO_APP
288+
; RV64D_NOPAIR-NEXT: ld s2, 24(sp) # 8-byte Folded Reload
289+
; RV64D_NOPAIR-NEXT: ld s3, 16(sp) # 8-byte Folded Reload
290+
; RV64D_NOPAIR-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
291+
; RV64D_NOPAIR-NEXT: ld s5, 0(sp) # 8-byte Folded Reload
292+
; RV64D_NOPAIR-NEXT: .cfi_restore s2
293+
; RV64D_NOPAIR-NEXT: .cfi_restore s3
294+
; RV64D_NOPAIR-NEXT: .cfi_restore s4
295+
; RV64D_NOPAIR-NEXT: .cfi_restore s5
296+
; RV64D_NOPAIR-NEXT: addi sp, sp, 32
297+
; RV64D_NOPAIR-NEXT: .cfi_def_cfa_offset 0
298+
; RV64D_NOPAIR-NEXT: ret
300299
entry:
301300
%arrayidx = getelementptr inbounds i8*, i8** %a, i64 1
302301
%0 = load i8*, i8** %arrayidx, align 8
@@ -308,203 +307,3 @@ entry:
308307
tail call void asm sideeffect "", "{x18},{x19},{x20},{x21}"(i8* %0, i8* %1, i8* %2, i8* %3)
309308
ret void
310309
}
311-
312-
313-
define dso_local void @testf(float* nocapture noundef readonly %a) local_unnamed_addr #0 {
314-
; RV32I-LABEL: testf:
315-
; RV32I: # %bb.0: # %entry
316-
; RV32I-NEXT: lw a3, 0(a0)
317-
; RV32I-NEXT: lw a4, 4(a0)
318-
; RV32I-NEXT: lw a2, 8(a0)
319-
; RV32I-NEXT: lw a1, 12(a0)
320-
; RV32I-NEXT: mv a0, a4
321-
; RV32I-NEXT: tail sinkf
322-
;
323-
; RV32D-LABEL: testf:
324-
; RV32D: # %bb.0: # %entry
325-
; RV32D-NEXT: flw fa3, 0(a0)
326-
; RV32D-NEXT: flw fa0, 4(a0)
327-
; RV32D-NEXT: flw fa2, 8(a0)
328-
; RV32D-NEXT: flw fa1, 12(a0)
329-
; RV32D-NEXT: tail sinkf
330-
;
331-
; RV64I-LABEL: testf:
332-
; RV64I: # %bb.0: # %entry
333-
; RV64I-NEXT: lw a3, 0(a0)
334-
; RV64I-NEXT: lw a4, 4(a0)
335-
; RV64I-NEXT: lw a2, 8(a0)
336-
; RV64I-NEXT: lw a1, 12(a0)
337-
; RV64I-NEXT: mv a0, a4
338-
; RV64I-NEXT: tail sinkf
339-
;
340-
; RV64D-LABEL: testf:
341-
; RV64D: # %bb.0: # %entry
342-
; RV64D-NEXT: flw fa3, 0(a0)
343-
; RV64D-NEXT: flw fa0, 4(a0)
344-
; RV64D-NEXT: flw fa2, 8(a0)
345-
; RV64D-NEXT: flw fa1, 12(a0)
346-
; RV64D-NEXT: tail sinkf
347-
;
348-
; RV32I_PAIR-LABEL: testf:
349-
; RV32I_PAIR: # %bb.0: # %entry
350-
; RV32I_PAIR-NEXT: lw a3, 0(a0)
351-
; RV32I_PAIR-NEXT: lw a4, 4(a0)
352-
; RV32I_PAIR-NEXT: lw a2, 8(a0)
353-
; RV32I_PAIR-NEXT: lw a1, 12(a0)
354-
; RV32I_PAIR-NEXT: mv a0, a4
355-
; RV32I_PAIR-NEXT: tail sinkf
356-
;
357-
; RV32D_PAIR-LABEL: testf:
358-
; RV32D_PAIR: # %bb.0: # %entry
359-
; RV32D_PAIR-NEXT: flw fa3, 0(a0)
360-
; RV32D_PAIR-NEXT: flw fa0, 4(a0)
361-
; RV32D_PAIR-NEXT: flw fa2, 8(a0)
362-
; RV32D_PAIR-NEXT: flw fa1, 12(a0)
363-
; RV32D_PAIR-NEXT: tail sinkf
364-
;
365-
; RV64I_PAIR-LABEL: testf:
366-
; RV64I_PAIR: # %bb.0: # %entry
367-
; RV64I_PAIR-NEXT: lw a3, 0(a0)
368-
; RV64I_PAIR-NEXT: lw a4, 4(a0)
369-
; RV64I_PAIR-NEXT: lw a2, 8(a0)
370-
; RV64I_PAIR-NEXT: lw a1, 12(a0)
371-
; RV64I_PAIR-NEXT: mv a0, a4
372-
; RV64I_PAIR-NEXT: tail sinkf
373-
;
374-
; RV64P_8700-LABEL: testf:
375-
; RV64P_8700: # %bb.0: # %entry
376-
; RV64P_8700-NEXT: flw fa3, 0(a0)
377-
; RV64P_8700-NEXT: flw fa0, 4(a0)
378-
; RV64P_8700-NEXT: flw fa2, 8(a0)
379-
; RV64P_8700-NEXT: flw fa1, 12(a0)
380-
; RV64P_8700-NEXT: tail sinkf
381-
;
382-
; RV64D_PAIR-LABEL: testf:
383-
; RV64D_PAIR: # %bb.0: # %entry
384-
; RV64D_PAIR-NEXT: flw fa3, 0(a0)
385-
; RV64D_PAIR-NEXT: flw fa0, 4(a0)
386-
; RV64D_PAIR-NEXT: flw fa2, 8(a0)
387-
; RV64D_PAIR-NEXT: flw fa1, 12(a0)
388-
; RV64D_PAIR-NEXT: tail sinkf
389-
;
390-
; RV64D_8700-LABEL: testf:
391-
; RV64D_8700: # %bb.0: # %entry
392-
; RV64D_8700-NEXT: flw fa3, 0(a0)
393-
; RV64D_8700-NEXT: flw fa0, 4(a0)
394-
; RV64D_8700-NEXT: flw fa2, 8(a0)
395-
; RV64D_8700-NEXT: flw fa1, 12(a0)
396-
; RV64D_8700-NEXT: tail sinkf
397-
entry:
398-
%arrayidx = getelementptr inbounds float, float* %a, i64 1
399-
%0 = load float, float* %arrayidx, align 4
400-
%arrayidx1 = getelementptr inbounds float, float* %a, i64 3
401-
%1 = load float, float* %arrayidx1, align 4
402-
%arrayidx2 = getelementptr inbounds float, float* %a, i64 2
403-
%2 = load float, float* %arrayidx2, align 4
404-
%3 = load float, float* %a, align 4
405-
tail call void @sinkf(float noundef %0, float noundef %1, float noundef %2, float noundef %3)
406-
ret void
407-
}
408-
409-
declare dso_local void @sinkf(float noundef, float noundef, float noundef, float noundef) local_unnamed_addr
410-
411-
define dso_local void @testd(double* nocapture noundef readonly %a) local_unnamed_addr #0 {
412-
; RV32I-LABEL: testd:
413-
; RV32I: # %bb.0: # %entry
414-
; RV32I-NEXT: lw a4, 16(a0)
415-
; RV32I-NEXT: lw a5, 20(a0)
416-
; RV32I-NEXT: lw a2, 24(a0)
417-
; RV32I-NEXT: lw a3, 28(a0)
418-
; RV32I-NEXT: lw a6, 0(a0)
419-
; RV32I-NEXT: lw a7, 4(a0)
420-
; RV32I-NEXT: lw t0, 8(a0)
421-
; RV32I-NEXT: lw a1, 12(a0)
422-
; RV32I-NEXT: mv a0, t0
423-
; RV32I-NEXT: tail sinkd
424-
;
425-
; RV32D-LABEL: testd:
426-
; RV32D: # %bb.0: # %entry
427-
; RV32D-NEXT: fld fa3, 0(a0)
428-
; RV32D-NEXT: fld fa0, 8(a0)
429-
; RV32D-NEXT: fld fa2, 16(a0)
430-
; RV32D-NEXT: fld fa1, 24(a0)
431-
; RV32D-NEXT: tail sinkd
432-
;
433-
; RV64I-LABEL: testd:
434-
; RV64I: # %bb.0: # %entry
435-
; RV64I-NEXT: ld a3, 0(a0)
436-
; RV64I-NEXT: ld a4, 8(a0)
437-
; RV64I-NEXT: ld a2, 16(a0)
438-
; RV64I-NEXT: ld a1, 24(a0)
439-
; RV64I-NEXT: mv a0, a4
440-
; RV64I-NEXT: tail sinkd
441-
;
442-
; RV64D-LABEL: testd:
443-
; RV64D: # %bb.0: # %entry
444-
; RV64D-NEXT: fld fa3, 0(a0)
445-
; RV64D-NEXT: fld fa0, 8(a0)
446-
; RV64D-NEXT: fld fa2, 16(a0)
447-
; RV64D-NEXT: fld fa1, 24(a0)
448-
; RV64D-NEXT: tail sinkd
449-
;
450-
; RV32I_PAIR-LABEL: testd:
451-
; RV32I_PAIR: # %bb.0: # %entry
452-
; RV32I_PAIR-NEXT: mips.lwp a4, a5, 16(a0)
453-
; RV32I_PAIR-NEXT: mips.lwp a2, a3, 24(a0)
454-
; RV32I_PAIR-NEXT: mips.lwp a6, a7, 0(a0)
455-
; RV32I_PAIR-NEXT: mips.lwp a0, a1, 8(a0)
456-
; RV32I_PAIR-NEXT: tail sinkd
457-
;
458-
; RV32D_PAIR-LABEL: testd:
459-
; RV32D_PAIR: # %bb.0: # %entry
460-
; RV32D_PAIR-NEXT: fld fa3, 0(a0)
461-
; RV32D_PAIR-NEXT: fld fa0, 8(a0)
462-
; RV32D_PAIR-NEXT: fld fa2, 16(a0)
463-
; RV32D_PAIR-NEXT: fld fa1, 24(a0)
464-
; RV32D_PAIR-NEXT: tail sinkd
465-
;
466-
; RV64I_PAIR-LABEL: testd:
467-
; RV64I_PAIR: # %bb.0: # %entry
468-
; RV64I_PAIR-NEXT: ld a3, 0(a0)
469-
; RV64I_PAIR-NEXT: ld a4, 8(a0)
470-
; RV64I_PAIR-NEXT: ld a2, 16(a0)
471-
; RV64I_PAIR-NEXT: ld a1, 24(a0)
472-
; RV64I_PAIR-NEXT: mv a0, a4
473-
; RV64I_PAIR-NEXT: tail sinkd
474-
;
475-
; RV64P_8700-LABEL: testd:
476-
; RV64P_8700: # %bb.0: # %entry
477-
; RV64P_8700-NEXT: fld fa3, 0(a0)
478-
; RV64P_8700-NEXT: fld fa0, 8(a0)
479-
; RV64P_8700-NEXT: fld fa2, 16(a0)
480-
; RV64P_8700-NEXT: fld fa1, 24(a0)
481-
; RV64P_8700-NEXT: tail sinkd
482-
;
483-
; RV64D_PAIR-LABEL: testd:
484-
; RV64D_PAIR: # %bb.0: # %entry
485-
; RV64D_PAIR-NEXT: fld fa3, 0(a0)
486-
; RV64D_PAIR-NEXT: fld fa0, 8(a0)
487-
; RV64D_PAIR-NEXT: fld fa2, 16(a0)
488-
; RV64D_PAIR-NEXT: fld fa1, 24(a0)
489-
; RV64D_PAIR-NEXT: tail sinkd
490-
;
491-
; RV64D_8700-LABEL: testd:
492-
; RV64D_8700: # %bb.0: # %entry
493-
; RV64D_8700-NEXT: fld fa3, 0(a0)
494-
; RV64D_8700-NEXT: fld fa0, 8(a0)
495-
; RV64D_8700-NEXT: fld fa2, 16(a0)
496-
; RV64D_8700-NEXT: fld fa1, 24(a0)
497-
; RV64D_8700-NEXT: tail sinkd
498-
entry:
499-
%arrayidx = getelementptr inbounds double, double* %a, i64 1
500-
%0 = load double, double* %arrayidx, align 8
501-
%arrayidx1 = getelementptr inbounds double, double* %a, i64 3
502-
%1 = load double, double* %arrayidx1, align 8
503-
%arrayidx2 = getelementptr inbounds double, double* %a, i64 2
504-
%2 = load double, double* %arrayidx2, align 8
505-
%3 = load double, double* %a, align 8
506-
tail call void @sinkd(double noundef %0, double noundef %1, double noundef %2, double noundef %3)
507-
ret void
508-
}
509-
510-
declare dso_local void @sinkd(double noundef, double noundef, double noundef, double noundef) local_unnamed_addr

0 commit comments

Comments
 (0)