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4 files changed

+261
-188
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4 files changed

+261
-188
lines changed

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5919,11 +5919,15 @@ bool AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(
59195919
Register LowHalf = B.buildOr(S64, ExtPointer, NumRecordsLHS).getReg(0);
59205920

59215921
// Build the higher 64-bit value, which has the higher 38-bit num_records,
5922-
// 6-bit zero (omit), 14-bit stride and 6-bit zero (omit).
5922+
// 6-bit zero (omit), 16-bit stride and scale and 4-bit flag.
59235923
auto NumRecordsRHS = B.buildLShr(S64, NumRecords, B.buildConstant(S32, 7));
59245924
auto ExtStride = B.buildAnyExt(S64, Stride);
59255925
auto ShiftedStride = B.buildShl(S64, ExtStride, B.buildConstant(S32, 44));
5926-
Register HighHalf = B.buildOr(S64, NumRecordsRHS, ShiftedStride).getReg(0);
5926+
auto ExtFlags = B.buildAnyExt(S64, Flags);
5927+
auto NewFlags = B.buildAnd(S64, ExtFlags, B.buildConstant(S64, 0x3));
5928+
auto ShiftedFlags = B.buildShl(S64, NewFlags, B.buildConstant(S32, 60));
5929+
auto CombinedFields = B.buildOr(S64, NumRecordsRHS, ShiftedStride);
5930+
Register HighHalf = B.buildOr(S64, CombinedFields, ShiftedFlags).getReg(0);
59275931
B.buildMergeValues(Result, {LowHalf, HighHalf});
59285932
} else {
59295933
NumRecords = B.buildTrunc(S32, NumRecords).getReg(0);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11615,16 +11615,24 @@ SDValue SITargetLowering::lowerPointerAsRsrcIntrin(SDNode *Op,
1161511615
DAG.getNode(ISD::OR, Loc, MVT::i64, ExtPointer, NumRecordsLHS);
1161611616

1161711617
// Build the higher 64-bit value, which has the higher 38-bit num_records,
11618-
// 6-bit zero (omit), 14-bit stride and 6-bit zero (omit).
11618+
// 6-bit zero (omit), 16-bit stride and scale and 4-bit flag.
1161911619
SDValue NumRecordsRHS =
1162011620
DAG.getNode(ISD::SRL, Loc, MVT::i64, NumRecords,
1162111621
DAG.getShiftAmountConstant(7, MVT::i32, Loc));
1162211622
SDValue ExtStride = DAG.getAnyExtOrTrunc(Stride, Loc, MVT::i64);
1162311623
SDValue ShiftedStride =
1162411624
DAG.getNode(ISD::SHL, Loc, MVT::i64, ExtStride,
1162511625
DAG.getShiftAmountConstant(44, MVT::i32, Loc));
11626-
SDValue HighHalf =
11626+
SDValue ExtFlags = DAG.getAnyExtOrTrunc(Flags, Loc, MVT::i64);
11627+
SDValue NewFlags = DAG.getNode(ISD::AND, Loc, MVT::i64, ExtFlags,
11628+
DAG.getConstant(0x3, Loc, MVT::i64));
11629+
SDValue ShiftedFlags =
11630+
DAG.getNode(ISD::SHL, Loc, MVT::i64, NewFlags,
11631+
DAG.getShiftAmountConstant(60, MVT::i32, Loc));
11632+
SDValue CombinedFields =
1162711633
DAG.getNode(ISD::OR, Loc, MVT::i64, NumRecordsRHS, ShiftedStride);
11634+
SDValue HighHalf =
11635+
DAG.getNode(ISD::OR, Loc, MVT::i64, CombinedFields, ShiftedFlags);
1162811636

1162911637
Rsrc = DAG.getNode(ISD::BUILD_VECTOR, Loc, MVT::v2i64, LowHalf, HighHalf);
1163011638
} else {

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