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Add tests
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‎llvm/test/CodeGen/RISCV/live-variables-basic.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=riscv-live-variables -verify-machineinstrs -o - %s | FileCheck %s
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#
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# Test basic live variable analysis with simple control flow and basic blocks
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--- |
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define i64 @test_simple_add(i64 %a, i64 %b) {
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entry:
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%sum = add i64 %a, %b
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ret i64 %sum
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}
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define i64 @test_if_then_else(i64 %a, i64 %b) {
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entry:
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%cmp = icmp sgt i64 %a, %b
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br i1 %cmp, label %then, label %else
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then:
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%mul = mul i64 %a, %b
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br label %end
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else:
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%sub = sub i64 %a, %b
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br label %end
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end:
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%result = phi i64 [ %mul, %then ], [ %sub, %else ]
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ret i64 %result
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}
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define i64 @test_multiple_uses(i64 %a, i64 %b, i64 %c) {
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entry:
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%t1 = add i64 %a, %b
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%t2 = mul i64 %t1, %c
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%t3 = sub i64 %t2, %a
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%t4 = add i64 %t3, %b
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ret i64 %t4
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}
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...
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---
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name: test_simple_add
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; CHECK-LABEL: name: test_simple_add
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $x10, $x11
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; Test that %0 and %1 are live-in, used once, and %2 is defined
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%0:gpr = COPY $x10
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%1:gpr = COPY $x11
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%2:gpr = ADD %0, %1
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$x10 = COPY %2
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PseudoRET implicit $x10
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...
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---
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name: test_if_then_else
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; CHECK-LABEL: name: test_if_then_else
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors
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; CHECK-NEXT: liveins: $x10, $x11
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; Test that %0 and %1 are live across multiple blocks
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%0:gpr = COPY $x10
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%1:gpr = COPY $x11
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%2:gpr = SLT %1, %0
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BEQ %2, $x0, %bb.2
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bb.1.then:
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; CHECK: bb.1.then:
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; %0 and %1 should be live-in here
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%3:gpr = MUL %0, %1
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PseudoBR %bb.3
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bb.2.else:
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; CHECK: bb.2.else:
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; %0 and %1 should be live-in here
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%4:gpr = SUB %0, %1
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PseudoBR %bb.3
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bb.3.end:
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; CHECK: bb.3.end:
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; Either %3 or %4 should be live-in (phi sources)
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%5:gpr = PHI %3, %bb.1, %4, %bb.2
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$x10 = COPY %5
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PseudoRET implicit $x10
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...
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---
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name: test_multiple_uses
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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- { reg: '$x12', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12
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; CHECK-LABEL: name: test_multiple_uses
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $x10, $x11, $x12
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; Test that variables with multiple uses have correct liveness ranges
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%0:gpr = COPY $x10
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%1:gpr = COPY $x11
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%2:gpr = COPY $x12
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; %0 used here and later
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%3:gpr = ADD %0, %1
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; %3 used in next instruction
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%4:gpr = MUL %3, %2
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; %0 used again here (should still be live)
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%5:gpr = SUB %4, %0
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; %1 used again here
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%6:gpr = ADD %5, %1
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$x10 = COPY %6
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/live-variables-calls.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=riscv-live-variables -verify-machineinstrs -o - %s | FileCheck %s
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#
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# Test live variable analysis with function calls and register clobbering
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# Function calls clobber caller-saved registers, which affects liveness
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--- |
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declare i64 @external_func(i64, i64)
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declare void @void_func(i64)
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define i64 @test_call_simple(i64 %a, i64 %b) {
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entry:
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%result = call i64 @external_func(i64 %a, i64 %b)
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ret i64 %result
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}
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define i64 @test_call_with_live_values(i64 %a, i64 %b, i64 %c) {
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entry:
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%sum1 = add i64 %a, %b
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%result = call i64 @external_func(i64 %sum1, i64 %c)
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; %b is live across the call
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%final = add i64 %result, %b
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ret i64 %final
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}
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define i64 @test_multiple_calls(i64 %a, i64 %b) {
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entry:
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%r1 = call i64 @external_func(i64 %a, i64 %b)
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call void @void_func(i64 %r1)
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%r2 = call i64 @external_func(i64 %r1, i64 %b)
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ret i64 %r2
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}
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define i64 @test_call_with_spill(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) {
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entry:
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%sum = add i64 %a, %b
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%result = call i64 @external_func(i64 %sum, i64 %c)
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; Many values live across call - may require spilling
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%t1 = add i64 %result, %d
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%t2 = add i64 %t1, %e
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%t3 = add i64 %t2, %f
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%t4 = add i64 %t3, %g
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%t5 = add i64 %t4, %h
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ret i64 %t5
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}
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...
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---
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name: test_call_simple
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; CHECK-LABEL: name: test_call_simple
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $x10, $x11
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%0:gpr = COPY $x10
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%1:gpr = COPY $x11
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$x10 = COPY %0
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$x11 = COPY %1
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; Call clobbers many registers per calling convention
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PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
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%2:gpr = COPY $x10
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$x10 = COPY %2
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PseudoRET implicit $x10
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...
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---
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name: test_call_with_live_values
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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- { reg: '$x12', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12
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; CHECK-LABEL: name: test_call_with_live_values
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $x10, $x11, $x12
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%0:gpr = COPY $x10
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%1:gpr = COPY $x11
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%2:gpr = COPY $x12
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%3:gpr = ADD %0, %1
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; %1 must remain live across this call
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$x10 = COPY %3
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$x11 = COPY %2
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PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
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%4:gpr = COPY $x10
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; %1 is used again here after the call
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%5:gpr = ADD %4, %1
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$x10 = COPY %5
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PseudoRET implicit $x10
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...
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---
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name: test_multiple_calls
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; CHECK-LABEL: name: test_multiple_calls
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $x10, $x11
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%0:gpr = COPY $x10
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%1:gpr = COPY $x11
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; First call
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$x10 = COPY %0
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$x11 = COPY %1
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PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
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%2:gpr = COPY $x10
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; Second call (void)
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$x10 = COPY %2
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PseudoCALL target-flags(riscv-call) @void_func, csr_ilp32_lp64, implicit-def $x1, implicit $x10
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; Third call - %2 and %1 are both live here
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$x10 = COPY %2
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$x11 = COPY %1
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PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
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%3:gpr = COPY $x10
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$x10 = COPY %3
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PseudoRET implicit $x10
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...
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---
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name: test_call_with_spill
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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- { id: 8, class: gpr }
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- { id: 9, class: gpr }
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- { id: 10, class: gpr }
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- { id: 11, class: gpr }
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- { id: 12, class: gpr }
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- { id: 13, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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- { reg: '$x12', virtual-reg: '%2' }
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- { reg: '$x13', virtual-reg: '%3' }
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- { reg: '$x14', virtual-reg: '%4' }
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- { reg: '$x15', virtual-reg: '%5' }
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- { reg: '$x16', virtual-reg: '%6' }
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- { reg: '$x17', virtual-reg: '%7' }
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; CHECK-LABEL: name: test_call_with_spill
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
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; Many registers live across call - tests register pressure
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%0:gpr = COPY $x10
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%1:gpr = COPY $x11
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%2:gpr = COPY $x12
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%3:gpr = COPY $x13
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%4:gpr = COPY $x14
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%5:gpr = COPY $x15
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%6:gpr = COPY $x16
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%7:gpr = COPY $x17
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%8:gpr = ADD %0, %1
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; Call with many live values - %3, %4, %5, %6, %7 all live across
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$x10 = COPY %8
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$x11 = COPY %2
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PseudoCALL target-flags(riscv-call) @external_func, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
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%9:gpr = COPY $x10
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; All these values should have been kept live
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%10:gpr = ADD %9, %3
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%11:gpr = ADD %10, %4
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%12:gpr = ADD %11, %5
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%13:gpr = ADD %12, %6
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%14:gpr = ADD %13, %7
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$x10 = COPY %14
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PseudoRET implicit $x10
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...

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