address comments

Author: AlexMaclean

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -11889,6 +11889,47 @@ bool TargetLowering::LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT,
       return true;
     }
 
+    // Special case: expand i1 comparisons using logical operations.
+    if (OpVT == MVT::i1) {
+      SDValue Ret;
+      switch (CCCode) {
+      default:
+        llvm_unreachable("Unknown integer setcc!");
+      case ISD::SETEQ: // X == Y  -->  ~(X ^ Y)
+        Ret = DAG.getNOT(dl, DAG.getNode(ISD::XOR, dl, MVT::i1, LHS, RHS),
+                         MVT::i1);
+        break;
+      case ISD::SETNE: // X != Y  -->  (X ^ Y)
+        Ret = DAG.getNode(ISD::XOR, dl, MVT::i1, LHS, RHS);
+        break;
+      case ISD::SETGT:  // X >s Y  -->  X == 0 & Y == 1  -->  ~X & Y
+      case ISD::SETULT: // X <u Y  -->  X == 0 & Y == 1  -->  ~X & Y
+        Ret = DAG.getNode(ISD::AND, dl, MVT::i1, RHS,
+                          DAG.getNOT(dl, LHS, MVT::i1));
+        break;
+      case ISD::SETLT:  // X <s Y  -->  X == 1 & Y == 0  -->  ~Y & X
+      case ISD::SETUGT: // X >u Y  -->  X == 1 & Y == 0  -->  ~Y & X
+        Ret = DAG.getNode(ISD::AND, dl, MVT::i1, LHS,
+                          DAG.getNOT(dl, RHS, MVT::i1));
+        break;
+      case ISD::SETULE: // X <=u Y  -->  X == 0 | Y == 1  -->  ~X | Y
+      case ISD::SETGE:  // X >=s Y  -->  X == 0 | Y == 1  -->  ~X | Y
+        Ret = DAG.getNode(ISD::OR, dl, MVT::i1, RHS,
+                          DAG.getNOT(dl, LHS, MVT::i1));
+        break;
+      case ISD::SETUGE: // X >=u Y  -->  X == 1 | Y == 0  -->  ~Y | X
+      case ISD::SETLE:  // X <=s Y  -->  X == 1 | Y == 0  -->  ~Y | X
+        Ret = DAG.getNode(ISD::OR, dl, MVT::i1, LHS,
+                          DAG.getNOT(dl, RHS, MVT::i1));
+        break;
+      }
+
+      LHS = DAG.getZExtOrTrunc(Ret, dl, VT);
+      RHS = SDValue();
+      CC = SDValue();
+      return true;
+    }
+
     ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
     unsigned Opc = 0;
     switch (CCCode) {

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -670,7 +670,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   setCondCodeAction({ISD::SETNE, ISD::SETEQ, ISD::SETUGE, ISD::SETULE,
                      ISD::SETUGT, ISD::SETULT, ISD::SETGT, ISD::SETLT,
                      ISD::SETGE, ISD::SETLE},
-                    MVT::i1, Custom);
+                    MVT::i1, Expand);
 
   // expand extload of vector of integers.
   setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i16,
@@ -2673,46 +2673,6 @@ SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
   }
 }
 
-// Lowers SETCC nodes that aren't directly supported by our arch.
-SDValue NVPTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
-  SDValue L = Op->getOperand(0);
-  SDValue R = Op->getOperand(1);
-
-  if (L.getValueType() != MVT::i1)
-    return SDValue();
-
-  SDLoc DL(Op);
-  SDValue Ret;
-  switch (cast<CondCodeSDNode>(Op->getOperand(2))->get()) {
-  default:
-    llvm_unreachable("Unknown integer setcc!");
-  case ISD::SETEQ: // X == Y  -> ~(X^Y)
-    Ret = DAG.getNOT(DL, DAG.getNode(ISD::XOR, DL, MVT::i1, L, R), MVT::i1);
-    break;
-  case ISD::SETNE: // X != Y   -->  (X^Y)
-    Ret = DAG.getNode(ISD::XOR, DL, MVT::i1, L, R);
-    break;
-  case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
-  case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
-    Ret = DAG.getNode(ISD::AND, DL, MVT::i1, R, DAG.getNOT(DL, L, MVT::i1));
-    break;
-  case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
-  case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
-    Ret = DAG.getNode(ISD::AND, DL, MVT::i1, L, DAG.getNOT(DL, R, MVT::i1));
-    break;
-  case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
-  case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
-    Ret = DAG.getNode(ISD::OR, DL, MVT::i1, R, DAG.getNOT(DL, L, MVT::i1));
-    break;
-  case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
-  case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
-    Ret = DAG.getNode(ISD::OR, DL, MVT::i1, L, DAG.getNOT(DL, R, MVT::i1));
-    break;
-  }
-
-  return DAG.getZExtOrTrunc(Ret, DL, Op.getValueType());
-}
-
 /// If the types match, convert the generic copysign to the NVPTXISD version,
 /// otherwise bail ensuring that mismatched cases are properly expaned.
 SDValue NVPTXTargetLowering::LowerFCOPYSIGN(SDValue Op,
@@ -2966,8 +2926,6 @@ NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     return LowerSTORE(Op, DAG);
   case ISD::LOAD:
     return LowerLOAD(Op, DAG);
-  case ISD::SETCC:
-    return LowerSETCC(Op, DAG);
   case ISD::SHL_PARTS:
     return LowerShiftLeftParts(Op, DAG);
   case ISD::SRA_PARTS:

llvm/lib/Target/NVPTX/NVPTXISelLowering.h

@@ -628,8 +628,6 @@ class NVPTXTargetLowering : public TargetLowering {
   SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
 
-  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
-
   SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;