Skip to content

Commit 142707b

Browse files
Pierre-vhPierre-vh
committed
Further reduce test
1 parent 8142cf3 commit 142707b

File tree

1 file changed

+52
-74
lines changed

1 file changed

+52
-74
lines changed

‎llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare-crash-splat.ll‎

Lines changed: 52 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -1,94 +1,72 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2-
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes="amdgpu-late-codegenprepare,verify" %s | FileCheck %s
2+
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-late-codegenprepare %s | FileCheck %s
33

44
; This crashed because the PHI with a splat was rejected, but then we marked the PHI
55
; as visited and tried to convert one of its user afterwards.
66

7-
define amdgpu_kernel void @widget(i1 %arg, <4 x i8> %arg1, i64 %arg2) {
7+
define amdgpu_kernel void @widget(ptr %arg, ptr %arg1, ptr %arg2) {
88
; CHECK-LABEL: define amdgpu_kernel void @widget(
9-
; CHECK-SAME: i1 [[ARG:%.*]], <4 x i8> [[ARG1:%.*]], i64 [[ARG2:%.*]]) {
9+
; CHECK-SAME: ptr [[ARG:%.*]], ptr [[ARG1:%.*]], ptr [[ARG2:%.*]]) {
1010
; CHECK-NEXT: [[BB:.*]]:
11-
; CHECK-NEXT: [[WIDGET_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
12-
; CHECK-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[WIDGET_KERNARG_SEGMENT]], i64 36
13-
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4
11+
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARG]], align 4
1412
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1
15-
; CHECK-NEXT: [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[WIDGET_KERNARG_SEGMENT]], i64 40
16-
; CHECK-NEXT: [[ARG1_LOAD:%.*]] = load <4 x i8>, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 8
17-
; CHECK-NEXT: [[ARG2_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[WIDGET_KERNARG_SEGMENT]], i64 44
18-
; CHECK-NEXT: [[ARG2_LOAD:%.*]] = load i64, ptr addrspace(4) [[ARG2_KERNARG_OFFSET]], align 4
19-
; CHECK-NEXT: br label %[[BB_3:.*]]
20-
; CHECK: [[BB_3]]:
21-
; CHECK-NEXT: [[PHI:%.*]] = phi ptr addrspace(1) [ null, %[[BB]] ], [ [[GETELEMENTPTR:%.*]], %[[BB_14:.*]] ]
22-
; CHECK-NEXT: [[PHI4:%.*]] = phi <4 x i8> [ splat (i8 1), %[[BB]] ], [ [[PHI15:%.*]], %[[BB_14]] ]
23-
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_6_PREHEADER:.*]], label %[[BB_5:.*]]
13+
; CHECK-NEXT: [[ARG1_LOAD:%.*]] = load <4 x i8>, ptr [[ARG1]], align 4
14+
; CHECK-NEXT: [[ARG2_LOAD:%.*]] = load i64, ptr [[ARG2]], align 4
15+
; CHECK-NEXT: br label %[[BB_1:.*]]
16+
; CHECK: [[BB_1]]:
17+
; CHECK-NEXT: [[PHI:%.*]] = phi ptr [ null, %[[BB]] ], [ [[ARG1]], %[[BB_6:.*]] ]
18+
; CHECK-NEXT: [[PHI4:%.*]] = phi <4 x i8> [ splat (i8 1), %[[BB]] ], [ [[PHI15:%.*]], %[[BB_6]] ]
19+
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_2:.*]], label %[[BB_6]]
20+
; CHECK: [[BB_2]]:
21+
; CHECK-NEXT: [[PHI7:%.*]] = phi <4 x i8> [ [[PHI13:%.*]], %[[BB_5:.*]] ], [ [[PHI4]], %[[BB_1]] ]
22+
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_4:.*]], label %[[BB_5]]
23+
; CHECK: [[BB_3:.*]]:
24+
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_4]], label %[[BB_EXIT:.*]]
25+
; CHECK: [[BB_4]]:
26+
; CHECK-NEXT: [[PHI11:%.*]] = phi <4 x i8> [ [[PHI7]], %[[BB_3]] ], [ zeroinitializer, %[[BB_2]] ]
27+
; CHECK-NEXT: store <4 x i8> [[PHI11]], ptr [[PHI]], align 1
28+
; CHECK-NEXT: br label %[[BB_5]]
2429
; CHECK: [[BB_5]]:
25-
; CHECK-NEXT: br label %[[BB_14]]
26-
; CHECK: [[BB_6_PREHEADER]]:
27-
; CHECK-NEXT: br label %[[BB_6:.*]]
30+
; CHECK-NEXT: [[PHI13]] = phi <4 x i8> [ zeroinitializer, %[[BB_4]] ], [ [[PHI7]], %[[BB_2]] ]
31+
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_2]], label %[[BB_6]]
2832
; CHECK: [[BB_6]]:
29-
; CHECK-NEXT: [[PHI7:%.*]] = phi <4 x i8> [ [[PHI13:%.*]], %[[BB_12:.*]] ], [ [[PHI4]], %[[BB_6_PREHEADER]] ]
30-
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_8:.*]], label %[[BB_12]]
31-
; CHECK: [[BB_8]]:
32-
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_10:.*]], label %[[BB_9:.*]]
33-
; CHECK: [[BB_9]]:
34-
; CHECK-NEXT: br label %[[BB_10]]
35-
; CHECK: [[BB_10]]:
36-
; CHECK-NEXT: [[PHI11:%.*]] = phi <4 x i8> [ [[PHI7]], %[[BB_9]] ], [ zeroinitializer, %[[BB_8]] ]
37-
; CHECK-NEXT: [[EXTRACTELEMENT:%.*]] = extractelement <4 x i8> [[PHI11]], i64 0
38-
; CHECK-NEXT: store i8 [[EXTRACTELEMENT]], ptr addrspace(1) [[PHI]], align 1
39-
; CHECK-NEXT: br label %[[BB_12]]
40-
; CHECK: [[BB_12]]:
41-
; CHECK-NEXT: [[PHI13]] = phi <4 x i8> [ zeroinitializer, %[[BB_10]] ], [ [[PHI7]], %[[BB_6]] ]
42-
; CHECK-NEXT: br i1 [[TMP1]], label %[[BB_6]], label %[[BB_14]]
43-
; CHECK: [[BB_14]]:
44-
; CHECK-NEXT: [[PHI15]] = phi <4 x i8> [ [[ARG1_LOAD]], %[[BB_5]] ], [ zeroinitializer, %[[BB_12]] ]
45-
; CHECK-NEXT: [[GETELEMENTPTR]] = getelementptr i8, ptr addrspace(1) [[PHI]], i64 [[ARG2_LOAD]]
46-
; CHECK-NEXT: br label %[[BB_3]]
33+
; CHECK-NEXT: [[PHI15]] = phi <4 x i8> [ [[ARG1_LOAD]], %[[BB_1]] ], [ zeroinitializer, %[[BB_5]] ]
34+
; CHECK-NEXT: br label %[[BB_1]]
35+
; CHECK: [[BB_EXIT]]:
36+
; CHECK-NEXT: ret void
4737
;
4838
bb:
49-
%widget.kernarg.segment = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
50-
%arg.kernarg.offset.align.down = getelementptr inbounds i8, ptr addrspace(4) %widget.kernarg.segment, i64 36
51-
%0 = load i32, ptr addrspace(4) %arg.kernarg.offset.align.down, align 4
52-
%1 = trunc i32 %0 to i1
53-
%arg1.kernarg.offset = getelementptr inbounds i8, ptr addrspace(4) %widget.kernarg.segment, i64 40
54-
%arg1.load = load <4 x i8>, ptr addrspace(4) %arg1.kernarg.offset, align 8
55-
%arg2.kernarg.offset = getelementptr inbounds i8, ptr addrspace(4) %widget.kernarg.segment, i64 44
56-
%arg2.load = load i64, ptr addrspace(4) %arg2.kernarg.offset, align 4
57-
br label %bb.3
39+
%ld = load i32, ptr %arg, align 4
40+
%ld.trunc = trunc i32 %ld to i1
41+
%arg1.load = load <4 x i8>, ptr %arg1, align 4
42+
%arg2.load = load i64, ptr %arg2, align 4
43+
br label %bb.1
5844

59-
bb.3: ; preds = %bb.14, %bb
60-
%phi = phi ptr addrspace(1) [ null, %bb ], [ %getelementptr, %bb.14 ]
61-
%phi4 = phi <4 x i8> [ splat (i8 1), %bb ], [ %phi15, %bb.14 ]
62-
br i1 %1, label %bb.6.preheader, label %bb.5
45+
bb.1:
46+
%phi = phi ptr [ null, %bb ], [ %arg1, %bb.6 ]
47+
%phi4 = phi <4 x i8> [ splat (i8 1), %bb ], [ %phi15, %bb.6 ]
48+
br i1 %ld.trunc, label %bb.2, label %bb.6
6349

64-
bb.5: ; preds = %bb.3
65-
br label %bb.14
50+
bb.2:
51+
%phi7 = phi <4 x i8> [ %phi13, %bb.5 ], [ %phi4, %bb.1 ]
52+
br i1 %ld.trunc, label %bb.4, label %bb.5
6653

67-
bb.6.preheader: ; preds = %bb.3
68-
br label %bb.6
54+
bb.3:
55+
br i1 %ld.trunc, label %bb.4, label %bb.exit
6956

70-
bb.6: ; preds = %bb.6.preheader, %bb.12
71-
%phi7 = phi <4 x i8> [ %phi13, %bb.12 ], [ %phi4, %bb.6.preheader ]
72-
br i1 %1, label %bb.8, label %bb.12
57+
bb.4:
58+
%phi11 = phi <4 x i8> [ %phi7, %bb.3 ], [ zeroinitializer, %bb.2 ]
59+
store <4 x i8> %phi11, ptr %phi, align 1
60+
br label %bb.5
7361

74-
bb.8: ; preds = %bb.6
75-
br i1 %1, label %bb.10, label %bb.9
62+
bb.5:
63+
%phi13 = phi <4 x i8> [ zeroinitializer, %bb.4 ], [ %phi7, %bb.2 ]
64+
br i1 %ld.trunc, label %bb.2, label %bb.6
7665

77-
bb.9: ; preds = %bb.8
78-
br label %bb.10
66+
bb.6:
67+
%phi15 = phi <4 x i8> [ %arg1.load, %bb.1 ], [ zeroinitializer, %bb.5 ]
68+
br label %bb.1
7969

80-
bb.10: ; preds = %bb.9, %bb.8
81-
%phi11 = phi <4 x i8> [ %phi7, %bb.9 ], [ zeroinitializer, %bb.8 ]
82-
%extractelement = extractelement <4 x i8> %phi11, i64 0
83-
store i8 %extractelement, ptr addrspace(1) %phi, align 1
84-
br label %bb.12
85-
86-
bb.12: ; preds = %bb.10, %bb.6
87-
%phi13 = phi <4 x i8> [ zeroinitializer, %bb.10 ], [ %phi7, %bb.6 ]
88-
br i1 %1, label %bb.6, label %bb.14
89-
90-
bb.14: ; preds = %bb.5, %bb.12
91-
%phi15 = phi <4 x i8> [ %arg1.load, %bb.5 ], [ zeroinitializer, %bb.12 ]
92-
%getelementptr = getelementptr i8, ptr addrspace(1) %phi, i64 %arg2.load
93-
br label %bb.3
70+
bb.exit:
71+
ret void
9472
}

0 commit comments

Comments
 (0)