@@ -949,6 +949,7 @@ def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
949949 let arguments = [Int1Ty];
950950 let result = Int1Ty;
951951 let stages = [Stages<DXIL1_0, [all_stages]>];
952+ let properties = [IsWave];
952953}
953954
954955def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
@@ -957,6 +958,7 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
957958 let arguments = [];
958959 let result = Int1Ty;
959960 let stages = [Stages<DXIL1_0, [all_stages]>];
961+ let properties = [IsWave];
960962}
961963
962964def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
@@ -966,6 +968,7 @@ def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
966968 let result = OverloadTy;
967969 let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty, Int64Ty]>];
968970 let stages = [Stages<DXIL1_0, [all_stages]>];
971+ let properties = [IsWave];
969972}
970973
971974def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
@@ -975,6 +978,7 @@ def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
975978 let result = Int32Ty;
976979 let stages = [Stages<DXIL1_0, [all_stages]>];
977980 let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
981+ let properties = [IsWave];
978982}
979983
980984def WaveAllBitCount : DXILOp<135, waveAllOp> {
@@ -983,6 +987,7 @@ def WaveAllBitCount : DXILOp<135, waveAllOp> {
983987 let arguments = [Int1Ty];
984988 let result = Int32Ty;
985989 let stages = [Stages<DXIL1_0, [all_stages]>];
990+ let properties = [IsWave];
986991}
987992
988993def Barrier : DXILOp<80, barrier> {
@@ -997,4 +1002,5 @@ def Barrier : DXILOp<80, barrier> {
9971002 let result = VoidTy;
9981003 let stages = [Stages<DXIL1_0, [compute, library]>];
9991004 let attributes = [Attributes<DXIL1_0, []>];
1005+ let properties = [IsBarrier];
10001006}
0 commit comments