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[NFC][lldb] Cleanup the ArchDefinitionEntry definitons. (#152618)
This patch has default initialization values for the "sub", "cpu_mask" and "sub_mask" member variables of the ArchDefinitionEntry structure. This can simplify and cleanup the ArchDefinitionEntry arrays by allowing those that don't override the values to not have to initialize the values in the definitions if they match the default values. This patchs also disables clang format to align the values in the columns for easier readability.
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‎lldb/source/Utility/ArchSpec.cpp‎

Lines changed: 61 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -260,9 +260,9 @@ static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
260260
struct ArchDefinitionEntry {
261261
ArchSpec::Core core;
262262
uint32_t cpu;
263-
uint32_t sub;
264-
uint32_t cpu_mask;
265-
uint32_t sub_mask;
263+
uint32_t sub = LLDB_INVALID_CPUTYPE;
264+
uint32_t cpu_mask = UINT32_MAX;
265+
uint32_t sub_mask = UINT32_MAX;
266266
};
267267

268268
struct ArchDefinition {
@@ -357,7 +357,8 @@ static const ArchDefinitionEntry g_macho_arch_entries[] = {
357357
{ArchSpec::eCore_riscv32, llvm::MachO::CPU_TYPE_RISCV, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
358358
// Catch any unknown mach architectures so we can always use the object and symbol mach-o files
359359
{ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
360-
{ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
360+
{ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}
361+
};
361362
// clang-format on
362363

363364
static const ArchDefinition g_macho_arch_def = {eArchTypeMachO,
@@ -369,98 +370,60 @@ static const ArchDefinition g_macho_arch_def = {eArchTypeMachO,
369370
// convert cpu type and subtypes to architecture names, and to convert
370371
// architecture names to cpu types and subtypes. The ordering is important and
371372
// allows the precedence to be set when the table is built.
373+
// clang-format off
372374
static const ArchDefinitionEntry g_elf_arch_entries[] = {
373-
{ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
374-
0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
375-
{ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
376-
0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
377-
{ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
378-
0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
379-
{ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
380-
0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
381-
{ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
382-
ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
383-
{ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
384-
ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
385-
{ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
386-
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
387-
{ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
388-
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
389-
{ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
390-
0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
391-
{ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
392-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
393-
{ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
394-
0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
395-
{ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
396-
0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
397-
{ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
398-
ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
399-
{ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
400-
ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
401-
{ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
402-
ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
403-
{ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
404-
ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
405-
{ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
406-
ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
407-
{ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
408-
0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
409-
{ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
410-
ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
411-
{ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
412-
ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
413-
{ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
414-
ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
415-
{ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
416-
ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
417-
{ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
418-
ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
419-
{ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE,
420-
0xFFFFFFFFu, 0xFFFFFFFFu}, // MSP430
421-
{ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
422-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
423-
{ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
424-
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
425-
{ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
426-
0xFFFFFFFFu}, // AVR
427-
{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
428-
ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
429-
{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
430-
ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
431-
{ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH,
432-
ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu,
433-
0xFFFFFFFFu}, // loongarch32
434-
{ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH,
435-
ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu,
436-
0xFFFFFFFFu}, // loongarch64
375+
{ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC }, // Sparc
376+
{ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386 }, // Intel 80386
377+
{ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU }, // Intel MCU // FIXME: is this correct?
378+
{ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC }, // PowerPC
379+
{ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, ArchSpec::eCore_ppc64le_generic}, // PowerPC64le
380+
{ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, ArchSpec::eCore_ppc64_generic}, // PowerPC64
381+
{ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM }, // ARM
382+
{ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64 }, // ARM64
383+
{ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390 }, // SystemZ
384+
{ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9 }, // SPARC V9
385+
{ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64 }, // AMD64
386+
{ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32}, // mips32
387+
{ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r2}, // mips32r2
388+
{ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r6}, // mips32r6
389+
{ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32el}, // mips32el
390+
{ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r2el}, // mips32r2el
391+
{ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32r6el}, // mips32r6el
392+
{ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64},
393+
{ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r2}, // mips64r2
394+
{ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r6}, // mips64r6
395+
{ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64el}, // mips64el
396+
{ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r2el}, // mips64r2el
397+
{ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64r6el}, // mips64r6el
398+
{ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430 }, // MSP430
399+
{ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON }, // HEXAGON
400+
{ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2}, // ARC
401+
{ArchSpec::eCore_avr, llvm::ELF::EM_AVR }, // AVR
402+
{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, ArchSpec::eRISCVSubType_riscv32}, // riscv32
403+
{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, ArchSpec::eRISCVSubType_riscv64}, // riscv64
404+
{ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH, ArchSpec::eLoongArchSubType_loongarch32}, // loongarch32
405+
{ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH, ArchSpec::eLoongArchSubType_loongarch64}, // loongarch64
437406
};
407+
// clang-format on
438408

439409
static const ArchDefinition g_elf_arch_def = {
440410
eArchTypeELF,
441411
std::size(g_elf_arch_entries),
442412
g_elf_arch_entries,
443413
"elf",
444414
};
445-
415+
// clang-format off
446416
static const ArchDefinitionEntry g_coff_arch_entries[] = {
447-
{ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
448-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
449-
{ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
450-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
451-
{ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
452-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
453-
{ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
454-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
455-
{ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
456-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
457-
{ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
458-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
459-
{ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
460-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
461-
{ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
462-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
417+
{ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386}, // Intel 80x86
418+
{ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC}, // PowerPC
419+
{ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP}, // PowerPC (with FPU)
420+
{ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM}, // ARM
421+
{ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT}, // ARMv7
422+
{ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB}, // ARMv7
423+
{ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64}, // AMD64
424+
{ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64} // ARM64
463425
};
426+
// clang-format on
464427

465428
static const ArchDefinition g_coff_arch_def = {
466429
eArchTypeCOFF,
@@ -469,11 +432,12 @@ static const ArchDefinition g_coff_arch_def = {
469432
"pe-coff",
470433
};
471434

435+
// clang-format off
472436
static const ArchDefinitionEntry g_xcoff_arch_entries[] = {
473-
{ArchSpec::eCore_ppc_generic, llvm::XCOFF::TCPU_COM, LLDB_INVALID_CPUTYPE,
474-
0xFFFFFFFFu, 0xFFFFFFFFu},
475-
{ArchSpec::eCore_ppc64_generic, llvm::XCOFF::TCPU_PPC64,
476-
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}};
437+
{ArchSpec::eCore_ppc_generic, llvm::XCOFF::TCPU_COM},
438+
{ArchSpec::eCore_ppc64_generic, llvm::XCOFF::TCPU_PPC64}
439+
};
440+
// clang-format on
477441

478442
static const ArchDefinition g_xcoff_arch_def = {
479443
eArchTypeXCOFF,
@@ -695,13 +659,9 @@ uint32_t ArchSpec::GetMachOCPUSubType() const {
695659
return LLDB_INVALID_CPUTYPE;
696660
}
697661

698-
uint32_t ArchSpec::GetDataByteSize() const {
699-
return 1;
700-
}
662+
uint32_t ArchSpec::GetDataByteSize() const { return 1; }
701663

702-
uint32_t ArchSpec::GetCodeByteSize() const {
703-
return 1;
704-
}
664+
uint32_t ArchSpec::GetCodeByteSize() const { return 1; }
705665

706666
llvm::Triple::ArchType ArchSpec::GetMachine() const {
707667
const CoreDefinition *core_def = FindCoreDefinition(m_core);
@@ -1170,8 +1130,8 @@ static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
11701130
break;
11711131

11721132
// v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1173-
// Cortex-M0 - ARMv6-M - armv6m
1174-
// Cortex-M3 - ARMv7-M - armv7m
1133+
// Cortex-M0 - ARMv6-M - armv6m
1134+
// Cortex-M3 - ARMv7-M - armv7m
11751135
// Cortex-M4 - ARMv7E-M - armv7em
11761136
case ArchSpec::eCore_arm_armv7em:
11771137
if (!enforce_exact_match) {
@@ -1188,8 +1148,8 @@ static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
11881148
break;
11891149

11901150
// v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1191-
// Cortex-M0 - ARMv6-M - armv6m
1192-
// Cortex-M3 - ARMv7-M - armv7m
1151+
// Cortex-M0 - ARMv6-M - armv6m
1152+
// Cortex-M3 - ARMv7-M - armv7m
11931153
// Cortex-M4 - ARMv7E-M - armv7em
11941154
case ArchSpec::eCore_arm_armv7m:
11951155
if (!enforce_exact_match) {
@@ -1206,8 +1166,8 @@ static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
12061166
break;
12071167

12081168
// v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1209-
// Cortex-M0 - ARMv6-M - armv6m
1210-
// Cortex-M3 - ARMv7-M - armv7m
1169+
// Cortex-M0 - ARMv6-M - armv6m
1170+
// Cortex-M3 - ARMv7-M - armv7m
12111171
// Cortex-M4 - ARMv7E-M - armv7em
12121172
case ArchSpec::eCore_arm_armv6m:
12131173
if (!enforce_exact_match) {
@@ -1434,7 +1394,6 @@ bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
14341394
return lhs_core < rhs_core;
14351395
}
14361396

1437-
14381397
bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
14391398
return lhs.GetCore() == rhs.GetCore();
14401399
}

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