@@ -1374,27 +1374,6 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
13741374 MachineInstr &NewMI = *std::prev (MII);
13751375 NewMI.setDebugLoc (DL);
13761376
1377- // In a situation like the following:
1378- //
1379- // undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable),
1380- // ; DefSubIdx = subreg
1381- // %3:reg = COPY %2 ; SrcIdx = DstIdx = 0
1382- // .... = SOMEINSTR %3:reg
1383- //
1384- // there are no subranges for %3 so after rematerialization we need
1385- // to explicitly create them. Undefined subranges are removed later on.
1386- if (DstReg.isVirtual () && DefSubIdx && !CP.getSrcIdx () && !CP.getDstIdx () &&
1387- MRI->shouldTrackSubRegLiveness (DstReg)) {
1388- LiveInterval &DstInt = LIS->getInterval (DstReg);
1389- if (!DstInt.hasSubRanges ()) {
1390- LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg (DstReg);
1391- LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask (DefSubIdx);
1392- LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
1393- DstInt.createSubRangeFrom (LIS->getVNInfoAllocator (), UsedLanes, DstInt);
1394- DstInt.createSubRangeFrom (LIS->getVNInfoAllocator (), UnusedLanes, DstInt);
1395- }
1396- }
1397-
13981377 // In a situation like the following:
13991378 // %0:subreg = instr ; DefMI, subreg = DstIdx
14001379 // %1 = copy %0:subreg ; CopyMI, SrcIdx = 0
@@ -1507,7 +1486,6 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
15071486 NewRC = TRI->getCommonSubClass (NewRC, DefRC);
15081487 assert (NewRC && " subreg chosen for remat incompatible with instruction" );
15091488 }
1510-
15111489 // Remap subranges to new lanemask and change register class.
15121490 LiveInterval &DstInt = LIS->getInterval (DstReg);
15131491 for (LiveInterval::SubRange &SR : DstInt.subranges ()) {
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