Add an extra testcase with duplicate implicitdefs and make sure that implicit-defs are unique.

Author: davemgreen

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

@@ -1387,15 +1387,23 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
         DefinedInBB.addReg(MOP.getReg());
 
   // Copy over any implicit-def operands. This is like MI.copyImplicitOps, but
-  // only copies implicit defs.
-  auto CopyImplicitOps = [&](MachineBasicBlock::iterator MI) {
+  // only copies implicit defs and makes sure that each operand is only added
+  // once in case of duplicates.
+  auto CopyImplicitOps = [&](MachineBasicBlock::iterator MI1,
+                             MachineBasicBlock::iterator MI2) {
+    SmallSetVector<Register, 4> Ops;
     for (const MachineOperand &MO :
-         llvm::drop_begin(MI->operands(), MI->getDesc().getNumOperands()))
+         llvm::drop_begin(MI1->operands(), MI1->getDesc().getNumOperands()))
       if (MO.isReg() && MO.isImplicit() && MO.isDef())
-        MIB.add(MO);
+        Ops.insert(MO.getReg());
+    for (const MachineOperand &MO :
+         llvm::drop_begin(MI2->operands(), MI2->getDesc().getNumOperands()))
+      if (MO.isReg() && MO.isImplicit() && MO.isDef())
+        Ops.insert(MO.getReg());
+    for (auto Op : Ops)
+      MIB.addDef(Op, RegState::Implicit);
   };
-  CopyImplicitOps(I);
-  CopyImplicitOps(Paired);
+  CopyImplicitOps(I, Paired);
 
   // Erase the old instructions.
   I->eraseFromParent();

llvm/test/CodeGen/AArch64/ldst-implicitop.mir

@@ -49,10 +49,32 @@ body:             |
     ; CHECK-NEXT: renamable $q5, renamable $q20 = LDPQi renamable $lr, 3, implicit-def $q4_q5, implicit-def $q20_q21 :: (load (s128))
     ; CHECK-NEXT: $q0 = ORRv16i8 $q4, killed $q4
     ; CHECK-NEXT: $q1 = ORRv16i8 $q5, killed $q5
+    ; CHECK-NEXT: $q2 = ORRv16i8 $q20, killed $q20
+    ; CHECK-NEXT: $q3 = ORRv16i8 $q21, killed $q21
     ; CHECK-NEXT: RET_ReallyLR
     renamable $q5 = LDRQui renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
     renamable $q20 = LDRQui renamable $lr, 4, implicit-def $q20_q21 :: (load (s128))
     $q0 = ORRv16i8 $q4, killed $q4
     $q1 = ORRv16i8 $q5, killed $q5
+    $q2 = ORRv16i8 $q20, killed $q20
+    $q3 = ORRv16i8 $q21, killed $q21
+    RET_ReallyLR
+...
+---
+name:            impdef_both_same
+body:             |
+  bb.0:
+    liveins: $lr
+    ; CHECK-LABEL: name: impdef_both_same
+    ; CHECK: liveins: $lr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: renamable $q5, renamable $q20 = LDPQi renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
+    ; CHECK-NEXT: $q0 = ORRv16i8 $q4, killed $q4
+    ; CHECK-NEXT: $q1 = ORRv16i8 $q5, killed $q5
+    ; CHECK-NEXT: RET_ReallyLR
+    renamable $q5 = LDRQui renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
+    renamable $q20 = LDRQui renamable $lr, 4, implicit-def $q4_q5 :: (load (s128))
+    $q0 = ORRv16i8 $q4, killed $q4
+    $q1 = ORRv16i8 $q5, killed $q5
     RET_ReallyLR
 ...