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Implement isAsmClobberable() and make r2 allocatable on AIX64 for some leaf functions.
1 parent 281d178 commit 153d1d9

13 files changed

+180
-137
lines changed

‎llvm/lib/Target/PowerPC/PPCFrameLowering.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2772,6 +2772,14 @@ void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
27722772
MCPhysReg Cand = CSRegs[i];
27732773
if (!SavedRegs.test(Cand))
27742774
continue;
2775+
// When R2/X2 is a CSR and not used for passing arguments, it is allocated
2776+
// earlier than other volatile registers. R2/X2 is not contiguous with
2777+
// R13/X13 to R31/X31.
2778+
if (Cand == PPC::X2 || Cand == PPC::R2) {
2779+
SavedRegs.set(Cand);
2780+
continue;
2781+
}
2782+
27752783
if (PPC::GPRCRegClass.contains(Cand) && Cand < LowestGPR)
27762784
LowestGPR = Cand;
27772785
else if (PPC::G8RCRegClass.contains(Cand) && Cand < LowestG8R)

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3434,6 +3434,8 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
34343434
if (Subtarget.hasAIXShLibTLSModelOpt())
34353435
updateForAIXShLibTLSModelOpt(Model, DAG, getTargetMachine());
34363436

3437+
setUsesTOCBasePtr(DAG);
3438+
34373439
bool IsTLSLocalExecModel = Model == TLSModel::LocalExec;
34383440

34393441
if (IsTLSLocalExecModel || Model == TLSModel::InitialExec) {

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp‎

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -380,23 +380,24 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
380380

381381
markSuperRegs(Reserved, PPC::VRSAVE);
382382

383+
const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
384+
bool UsesTOCBasePtr = FuncInfo->usesTOCBasePtr();
383385
// The SVR4 ABI reserves r2 and r13
384386
if (Subtarget.isSVR4ABI()) {
385387
// We only reserve r2 if we need to use the TOC pointer. If we have no
386388
// explicit uses of the TOC pointer (meaning we're a leaf function with
387389
// no constant-pool loads, etc.) and we have no potential uses inside an
388390
// inline asm block, then we can treat r2 has an ordinary callee-saved
389391
// register.
390-
const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
391-
if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
392-
markSuperRegs(Reserved, PPC::R2); // System-reserved register
393-
markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
392+
if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
393+
markSuperRegs(Reserved, PPC::R2); // System-reserved register.
394+
markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register.
394395
}
395396

396-
// Always reserve r2 on AIX for now.
397-
// TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
398397
if (Subtarget.isAIXABI())
399-
markSuperRegs(Reserved, PPC::R2); // System-reserved register
398+
// We only reserve r2 if we need to use the TOC pointer on AIX.
399+
if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
400+
markSuperRegs(Reserved, PPC::R2); // System-reserved register.
400401

401402
// On PPC64, r13 is the thread pointer. Never allocate this register.
402403
if (TM.isPPC64())
@@ -441,14 +442,12 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
441442

442443
bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF,
443444
MCRegister PhysReg) const {
444-
// We cannot use getReservedRegs() to find the registers that are not asm
445-
// clobberable because there are some reserved registers which can be
446-
// clobbered by inline asm. For example, when LR is clobbered, the register is
447-
// saved and restored. We will hardcode the registers that are not asm
448-
// cloberable in this function.
449-
450-
// The stack pointer (R1/X1) is not clobberable by inline asm
451-
return PhysReg != PPC::R1 && PhysReg != PPC::X1;
445+
// CTR and LR registers are always reserved, but they are asm clobberable.
446+
if (PhysReg == PPC::CTR || PhysReg == PPC::CTR8 || PhysReg == PPC::LR ||
447+
PhysReg == PPC::LR8)
448+
return true;
449+
450+
return !getReservedRegs(MF).test(PhysReg);
452451
}
453452

454453
bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {

‎llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1146,11 +1146,11 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
11461146
; 64BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.1, implicit-def $x11 :: (load (s32) from %fixed-stack.1)
11471147
; 64BIT-NEXT: renamable $x12 = LWZ8 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4)
11481148
; 64BIT-NEXT: renamable $x0 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0)
1149-
; 64BIT-NEXT: renamable $x31 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2)
1150-
; 64BIT-NEXT: renamable $x30 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
1151-
; 64BIT-NEXT: renamable $r29 = LWZ 0, %fixed-stack.5, implicit-def $x29 :: (load (s32) from %fixed-stack.5)
1152-
; 64BIT-NEXT: renamable $x28 = LWA 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6)
1153-
; 64BIT-NEXT: renamable $x27 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16)
1149+
; 64BIT-NEXT: renamable $x2 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2)
1150+
; 64BIT-NEXT: renamable $x31 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
1151+
; 64BIT-NEXT: renamable $r30 = LWZ 0, %fixed-stack.5, implicit-def $x30 :: (load (s32) from %fixed-stack.5)
1152+
; 64BIT-NEXT: renamable $x29 = LWA 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6)
1153+
; 64BIT-NEXT: renamable $x28 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16)
11541154
; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
11551155
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
11561156
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6
@@ -1159,12 +1159,12 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
11591159
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r9, implicit killed $x9
11601160
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r10, implicit killed $x10
11611161
; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3
1162-
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x27
11631162
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x28
11641163
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x29
1165-
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x12
11661164
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x30
1165+
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x12
11671166
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x31
1167+
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x2
11681168
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x11
11691169
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x0
11701170
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3

‎llvm/test/CodeGen/PowerPC/aix-cc-abi.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1240,19 +1240,19 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
12401240
; ASM64PWR4-NEXT: lwz 5, 132(1)
12411241
; ASM64PWR4-NEXT: add 3, 3, 4
12421242
; ASM64PWR4-NEXT: add 3, 3, 12
1243-
; ASM64PWR4-NEXT: std 31, -8(1) # 8-byte Folded Spill
1243+
; ASM64PWR4-NEXT: std 2, -8(1) # 8-byte Folded Spill
12441244
; ASM64PWR4-NEXT: add 3, 3, 5
1245-
; ASM64PWR4-NEXT: lwz 31, 140(1)
1245+
; ASM64PWR4-NEXT: lwz 2, 140(1)
12461246
; ASM64PWR4-NEXT: lwa 11, 148(1)
1247-
; ASM64PWR4-NEXT: add 3, 3, 31
1247+
; ASM64PWR4-NEXT: add 3, 3, 2
12481248
; ASM64PWR4-NEXT: add 3, 3, 11
12491249
; ASM64PWR4-NEXT: ld 4, 152(1)
12501250
; ASM64PWR4-NEXT: lwz 0, 164(1)
12511251
; ASM64PWR4-NEXT: add 3, 3, 4
12521252
; ASM64PWR4-NEXT: lwa 5, 172(1)
12531253
; ASM64PWR4-NEXT: add 3, 3, 0
12541254
; ASM64PWR4-NEXT: add 3, 3, 5
1255-
; ASM64PWR4-NEXT: ld 31, -8(1) # 8-byte Folded Reload
1255+
; ASM64PWR4-NEXT: ld 2, -8(1) # 8-byte Folded Reload
12561256
; ASM64PWR4-NEXT: blr
12571257
entry:
12581258
%add = add nsw i32 %i1, %i2

‎llvm/test/CodeGen/PowerPC/aix-inline-asm-clobber-warning.ll‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
; RUN: llc < %s -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
2+
; RUN: -mcpu=pwr7 -mattr=+altivec -O0 2>&1 | FileCheck %s
3+
4+
; CHECK: warning: inline asm clobber list contains reserved registers: R2
5+
; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
6+
7+
@a = external global i32, align 4
8+
9+
define void @bar() {
10+
store i32 0, ptr @a, align 4
11+
call void asm sideeffect "li 2, 1", "~{r2}"()
12+
ret void
13+
}

‎llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,5 @@ body: |
1717
BLR8 implicit $lr8, implicit undef $rm, implicit $x3, implicit $f1
1818
...
1919
# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
20-
# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x1
21-
# CHECK-DAG: 4 ]
22-
# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
20+
# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x2 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 ]
21+
# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]

‎llvm/test/CodeGen/PowerPC/inc-of-add.ll‎

Lines changed: 63 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -166,81 +166,81 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
166166
;
167167
; AIX-PPC64-LABEL: vector_i128_i8:
168168
; AIX-PPC64: # %bb.0:
169-
; AIX-PPC64-NEXT: std 22, -80(1) # 8-byte Folded Spill
170-
; AIX-PPC64-NEXT: lbz 22, 207(1)
171169
; AIX-PPC64-NEXT: std 23, -72(1) # 8-byte Folded Spill
170+
; AIX-PPC64-NEXT: lbz 23, 207(1)
172171
; AIX-PPC64-NEXT: std 24, -64(1) # 8-byte Folded Spill
173-
; AIX-PPC64-NEXT: std 26, -48(1) # 8-byte Folded Spill
174172
; AIX-PPC64-NEXT: std 25, -56(1) # 8-byte Folded Spill
173+
; AIX-PPC64-NEXT: std 27, -40(1) # 8-byte Folded Spill
174+
; AIX-PPC64-NEXT: std 26, -48(1) # 8-byte Folded Spill
175+
; AIX-PPC64-NEXT: std 30, -16(1) # 8-byte Folded Spill
175176
; AIX-PPC64-NEXT: std 29, -24(1) # 8-byte Folded Spill
176177
; AIX-PPC64-NEXT: std 28, -32(1) # 8-byte Folded Spill
177-
; AIX-PPC64-NEXT: std 27, -40(1) # 8-byte Folded Spill
178+
; AIX-PPC64-NEXT: std 2, -80(1) # 8-byte Folded Spill
178179
; AIX-PPC64-NEXT: std 31, -8(1) # 8-byte Folded Spill
179-
; AIX-PPC64-NEXT: std 30, -16(1) # 8-byte Folded Spill
180-
; AIX-PPC64-NEXT: lbz 23, 199(1)
181-
; AIX-PPC64-NEXT: lbz 24, 191(1)
182-
; AIX-PPC64-NEXT: add 6, 22, 6
183-
; AIX-PPC64-NEXT: lbz 22, 231(1)
184-
; AIX-PPC64-NEXT: add 5, 23, 5
185-
; AIX-PPC64-NEXT: lbz 23, 223(1)
186-
; AIX-PPC64-NEXT: add 4, 24, 4
187-
; AIX-PPC64-NEXT: lbz 24, 215(1)
188-
; AIX-PPC64-NEXT: add 9, 22, 9
189-
; AIX-PPC64-NEXT: lbz 26, 127(1)
190-
; AIX-PPC64-NEXT: add 8, 23, 8
191-
; AIX-PPC64-NEXT: lbz 22, 255(1)
192-
; AIX-PPC64-NEXT: add 7, 24, 7
193-
; AIX-PPC64-NEXT: lbz 25, 119(1)
180+
; AIX-PPC64-NEXT: lbz 24, 199(1)
181+
; AIX-PPC64-NEXT: lbz 25, 191(1)
182+
; AIX-PPC64-NEXT: add 6, 23, 6
183+
; AIX-PPC64-NEXT: lbz 23, 231(1)
184+
; AIX-PPC64-NEXT: add 5, 24, 5
185+
; AIX-PPC64-NEXT: lbz 24, 223(1)
186+
; AIX-PPC64-NEXT: add 4, 25, 4
187+
; AIX-PPC64-NEXT: lbz 25, 215(1)
188+
; AIX-PPC64-NEXT: add 9, 23, 9
189+
; AIX-PPC64-NEXT: lbz 27, 127(1)
190+
; AIX-PPC64-NEXT: add 8, 24, 8
191+
; AIX-PPC64-NEXT: lbz 23, 255(1)
192+
; AIX-PPC64-NEXT: add 7, 25, 7
193+
; AIX-PPC64-NEXT: lbz 26, 119(1)
194194
; AIX-PPC64-NEXT: addi 9, 9, 1
195-
; AIX-PPC64-NEXT: lbz 23, 247(1)
196-
; AIX-PPC64-NEXT: add 26, 22, 26
197-
; AIX-PPC64-NEXT: lbz 24, 239(1)
195+
; AIX-PPC64-NEXT: lbz 24, 247(1)
196+
; AIX-PPC64-NEXT: add 27, 23, 27
197+
; AIX-PPC64-NEXT: lbz 25, 239(1)
198198
; AIX-PPC64-NEXT: addi 8, 8, 1
199-
; AIX-PPC64-NEXT: lbz 29, 151(1)
200-
; AIX-PPC64-NEXT: add 25, 23, 25
201-
; AIX-PPC64-NEXT: lbz 22, 279(1)
202-
; AIX-PPC64-NEXT: add 10, 24, 10
203-
; AIX-PPC64-NEXT: lbz 28, 143(1)
199+
; AIX-PPC64-NEXT: lbz 30, 151(1)
200+
; AIX-PPC64-NEXT: add 26, 24, 26
201+
; AIX-PPC64-NEXT: lbz 23, 279(1)
202+
; AIX-PPC64-NEXT: add 10, 25, 10
203+
; AIX-PPC64-NEXT: lbz 29, 143(1)
204204
; AIX-PPC64-NEXT: addi 10, 10, 1
205-
; AIX-PPC64-NEXT: lbz 23, 271(1)
206-
; AIX-PPC64-NEXT: add 29, 22, 29
207-
; AIX-PPC64-NEXT: lbz 27, 135(1)
205+
; AIX-PPC64-NEXT: lbz 24, 271(1)
206+
; AIX-PPC64-NEXT: add 30, 23, 30
207+
; AIX-PPC64-NEXT: lbz 28, 135(1)
208208
; AIX-PPC64-NEXT: addi 7, 7, 1
209-
; AIX-PPC64-NEXT: lbz 24, 263(1)
210-
; AIX-PPC64-NEXT: add 28, 23, 28
209+
; AIX-PPC64-NEXT: lbz 25, 263(1)
210+
; AIX-PPC64-NEXT: add 29, 24, 29
211211
; AIX-PPC64-NEXT: lbz 11, 183(1)
212212
; AIX-PPC64-NEXT: addi 6, 6, 1
213-
; AIX-PPC64-NEXT: lbz 22, 311(1)
214-
; AIX-PPC64-NEXT: add 27, 24, 27
213+
; AIX-PPC64-NEXT: lbz 23, 311(1)
214+
; AIX-PPC64-NEXT: add 28, 25, 28
215215
; AIX-PPC64-NEXT: lbz 12, 175(1)
216216
; AIX-PPC64-NEXT: addi 5, 5, 1
217217
; AIX-PPC64-NEXT: lbz 0, 303(1)
218-
; AIX-PPC64-NEXT: add 11, 22, 11
219-
; AIX-PPC64-NEXT: lbz 31, 167(1)
218+
; AIX-PPC64-NEXT: add 11, 23, 11
219+
; AIX-PPC64-NEXT: lbz 2, 167(1)
220220
; AIX-PPC64-NEXT: addi 11, 11, 1
221-
; AIX-PPC64-NEXT: lbz 23, 295(1)
221+
; AIX-PPC64-NEXT: lbz 24, 295(1)
222222
; AIX-PPC64-NEXT: add 12, 0, 12
223-
; AIX-PPC64-NEXT: lbz 30, 159(1)
223+
; AIX-PPC64-NEXT: lbz 31, 159(1)
224224
; AIX-PPC64-NEXT: addi 4, 4, 1
225-
; AIX-PPC64-NEXT: lbz 24, 287(1)
226-
; AIX-PPC64-NEXT: add 31, 23, 31
225+
; AIX-PPC64-NEXT: lbz 25, 287(1)
226+
; AIX-PPC64-NEXT: add 2, 24, 2
227227
; AIX-PPC64-NEXT: stb 11, 15(3)
228228
; AIX-PPC64-NEXT: addi 11, 12, 1
229-
; AIX-PPC64-NEXT: add 30, 24, 30
229+
; AIX-PPC64-NEXT: add 31, 25, 31
230230
; AIX-PPC64-NEXT: stb 11, 14(3)
231-
; AIX-PPC64-NEXT: addi 11, 31, 1
231+
; AIX-PPC64-NEXT: addi 11, 2, 1
232232
; AIX-PPC64-NEXT: stb 11, 13(3)
233-
; AIX-PPC64-NEXT: addi 11, 30, 1
233+
; AIX-PPC64-NEXT: addi 11, 31, 1
234234
; AIX-PPC64-NEXT: stb 11, 12(3)
235-
; AIX-PPC64-NEXT: addi 11, 29, 1
235+
; AIX-PPC64-NEXT: addi 11, 30, 1
236236
; AIX-PPC64-NEXT: stb 11, 11(3)
237-
; AIX-PPC64-NEXT: addi 11, 28, 1
237+
; AIX-PPC64-NEXT: addi 11, 29, 1
238238
; AIX-PPC64-NEXT: stb 11, 10(3)
239-
; AIX-PPC64-NEXT: addi 11, 27, 1
239+
; AIX-PPC64-NEXT: addi 11, 28, 1
240240
; AIX-PPC64-NEXT: stb 11, 9(3)
241-
; AIX-PPC64-NEXT: addi 11, 26, 1
241+
; AIX-PPC64-NEXT: addi 11, 27, 1
242242
; AIX-PPC64-NEXT: stb 11, 8(3)
243-
; AIX-PPC64-NEXT: addi 11, 25, 1
243+
; AIX-PPC64-NEXT: addi 11, 26, 1
244244
; AIX-PPC64-NEXT: stb 11, 7(3)
245245
; AIX-PPC64-NEXT: stb 10, 6(3)
246246
; AIX-PPC64-NEXT: stb 9, 5(3)
@@ -249,6 +249,7 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
249249
; AIX-PPC64-NEXT: stb 6, 2(3)
250250
; AIX-PPC64-NEXT: stb 5, 1(3)
251251
; AIX-PPC64-NEXT: stb 4, 0(3)
252+
; AIX-PPC64-NEXT: ld 2, -80(1) # 8-byte Folded Reload
252253
; AIX-PPC64-NEXT: ld 31, -8(1) # 8-byte Folded Reload
253254
; AIX-PPC64-NEXT: ld 30, -16(1) # 8-byte Folded Reload
254255
; AIX-PPC64-NEXT: ld 29, -24(1) # 8-byte Folded Reload
@@ -258,7 +259,6 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
258259
; AIX-PPC64-NEXT: ld 25, -56(1) # 8-byte Folded Reload
259260
; AIX-PPC64-NEXT: ld 24, -64(1) # 8-byte Folded Reload
260261
; AIX-PPC64-NEXT: ld 23, -72(1) # 8-byte Folded Reload
261-
; AIX-PPC64-NEXT: ld 22, -80(1) # 8-byte Folded Reload
262262
; AIX-PPC64-NEXT: blr
263263
;
264264
; PPC64LE-LABEL: vector_i128_i8:
@@ -314,30 +314,30 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
314314
;
315315
; AIX-PPC64-LABEL: vector_i128_i16:
316316
; AIX-PPC64: # %bb.0:
317-
; AIX-PPC64-NEXT: std 26, -48(1) # 8-byte Folded Spill
318317
; AIX-PPC64-NEXT: std 27, -40(1) # 8-byte Folded Spill
319318
; AIX-PPC64-NEXT: std 28, -32(1) # 8-byte Folded Spill
320319
; AIX-PPC64-NEXT: std 29, -24(1) # 8-byte Folded Spill
321320
; AIX-PPC64-NEXT: std 30, -16(1) # 8-byte Folded Spill
322321
; AIX-PPC64-NEXT: std 31, -8(1) # 8-byte Folded Spill
322+
; AIX-PPC64-NEXT: std 2, -48(1) # 8-byte Folded Spill
323323
; AIX-PPC64-NEXT: lhz 11, 118(1)
324324
; AIX-PPC64-NEXT: lhz 12, 182(1)
325325
; AIX-PPC64-NEXT: lhz 0, 174(1)
326-
; AIX-PPC64-NEXT: lhz 31, 166(1)
326+
; AIX-PPC64-NEXT: lhz 2, 166(1)
327327
; AIX-PPC64-NEXT: add 11, 12, 11
328-
; AIX-PPC64-NEXT: lhz 30, 158(1)
328+
; AIX-PPC64-NEXT: lhz 31, 158(1)
329329
; AIX-PPC64-NEXT: add 10, 0, 10
330-
; AIX-PPC64-NEXT: lhz 29, 142(1)
331-
; AIX-PPC64-NEXT: add 9, 31, 9
332-
; AIX-PPC64-NEXT: lhz 28, 126(1)
333-
; AIX-PPC64-NEXT: add 8, 30, 8
334-
; AIX-PPC64-NEXT: lhz 27, 134(1)
335-
; AIX-PPC64-NEXT: add 6, 29, 6
336-
; AIX-PPC64-NEXT: lhz 26, 150(1)
337-
; AIX-PPC64-NEXT: add 4, 28, 4
338-
; AIX-PPC64-NEXT: add 5, 27, 5
330+
; AIX-PPC64-NEXT: lhz 30, 142(1)
331+
; AIX-PPC64-NEXT: add 9, 2, 9
332+
; AIX-PPC64-NEXT: lhz 29, 126(1)
333+
; AIX-PPC64-NEXT: add 8, 31, 8
334+
; AIX-PPC64-NEXT: lhz 28, 134(1)
335+
; AIX-PPC64-NEXT: add 6, 30, 6
336+
; AIX-PPC64-NEXT: lhz 27, 150(1)
337+
; AIX-PPC64-NEXT: add 4, 29, 4
338+
; AIX-PPC64-NEXT: add 5, 28, 5
339339
; AIX-PPC64-NEXT: addi 11, 11, 1
340-
; AIX-PPC64-NEXT: add 7, 26, 7
340+
; AIX-PPC64-NEXT: add 7, 27, 7
341341
; AIX-PPC64-NEXT: addi 10, 10, 1
342342
; AIX-PPC64-NEXT: addi 9, 9, 1
343343
; AIX-PPC64-NEXT: addi 8, 8, 1
@@ -353,12 +353,12 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
353353
; AIX-PPC64-NEXT: sth 6, 4(3)
354354
; AIX-PPC64-NEXT: sth 5, 2(3)
355355
; AIX-PPC64-NEXT: sth 4, 0(3)
356+
; AIX-PPC64-NEXT: ld 2, -48(1) # 8-byte Folded Reload
356357
; AIX-PPC64-NEXT: ld 31, -8(1) # 8-byte Folded Reload
357358
; AIX-PPC64-NEXT: ld 30, -16(1) # 8-byte Folded Reload
358359
; AIX-PPC64-NEXT: ld 29, -24(1) # 8-byte Folded Reload
359360
; AIX-PPC64-NEXT: ld 28, -32(1) # 8-byte Folded Reload
360361
; AIX-PPC64-NEXT: ld 27, -40(1) # 8-byte Folded Reload
361-
; AIX-PPC64-NEXT: ld 26, -48(1) # 8-byte Folded Reload
362362
; AIX-PPC64-NEXT: blr
363363
;
364364
; PPC64LE-LABEL: vector_i128_i16:

‎llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc-unknown-unkown \
2-
; RUN: -mcpu=pwr7 2>&1 | FileCheck %s
2+
; RUN: -mcpu=pwr7 -O0 2>&1 | FileCheck %s
33
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-unkown \
4-
; RUN: -mcpu=pwr7 2>&1 | FileCheck %s
4+
; RUN: -mcpu=pwr7 -O0 2>&1 | FileCheck %s
55

66
define void @test_r1_clobber() {
77
entry:
@@ -20,3 +20,24 @@ entry:
2020

2121
; CHECK: warning: inline asm clobber list contains reserved registers: X1
2222
; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
23+
24+
; CHECK: warning: inline asm clobber list contains reserved registers: R31
25+
; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
26+
27+
@a = dso_local global i32 100, align 4
28+
define dso_local signext i32 @main() {
29+
entry:
30+
%retval = alloca i32, align 4
31+
%old = alloca i64, align 8
32+
store i32 0, ptr %retval, align 4
33+
call void asm sideeffect "li 31, 1", "~{r31}"()
34+
call void asm sideeffect "li 30, 1", "~{r30}"()
35+
%0 = call i64 asm sideeffect "mr $0, 31", "=r"()
36+
store i64 %0, ptr %old, align 8
37+
%1 = load i32, ptr @a, align 4
38+
%conv = sext i32 %1 to i64
39+
%2 = alloca i8, i64 %conv, align 16
40+
%3 = load i64, ptr %old, align 8
41+
%conv1 = trunc i64 %3 to i32
42+
ret i32 %conv1
43+
}

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