[AggressiveInstCombine] Remove unnecessarily repeated tests. NFC.

Author: Cancelll

llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll

@@ -1802,302 +1802,6 @@ define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
   ret i32 %o2
 }
 
-define i32 @loadCombine_4consecutive_mixsize3(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_mixsize3(
-; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
-; LE-NEXT:    ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_4consecutive_mixsize3(
-; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; BE-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT:    [[L2:%.*]] = load i16, ptr [[P1]], align 2
-; BE-NEXT:    [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; BE-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT:    [[E2:%.*]] = zext i16 [[L2]] to i32
-; BE-NEXT:    [[E3:%.*]] = zext i8 [[L3]] to i32
-; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT:    [[S3:%.*]] = shl i32 [[E3]], 24
-; BE-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT:    [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; BE-NEXT:    ret i32 [[O2]]
-;
-  %p1 = getelementptr i8, ptr %p, i32 1
-  %p2 = getelementptr i8, ptr %p, i32 3
-  %l1 = load i8, ptr %p
-  %l2 = load i16, ptr %p1
-  %l3 = load i8, ptr %p2
-
-  %e1 = zext i8 %l1 to i32
-  %e2 = zext i16 %l2 to i32
-  %e3 = zext i8 %l3 to i32
-
-  %s2 = shl i32 %e2, 8
-  %s3 = shl i32 %e3, 24
-
-  %o1 = or i32 %e1, %s2
-  %o2 = or i32 %o1, %s3
-  ret i32 %o2
-}
-
-define i16 @loadCombine_mixsize_4bit(ptr %p) {
-; ALL-LABEL: @loadCombine_mixsize_4bit(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[P2:%.*]] = getelementptr i4, ptr [[P]], i32 3
-; ALL-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
-; ALL-NEXT:    [[L2:%.*]] = load i4, ptr [[P1]], align 1
-; ALL-NEXT:    [[L3:%.*]] = load i4, ptr [[P2]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i16
-; ALL-NEXT:    [[E2:%.*]] = zext i4 [[L2]] to i16
-; ALL-NEXT:    [[E3:%.*]] = zext i4 [[L3]] to i16
-; ALL-NEXT:    [[S2:%.*]] = shl i16 [[E2]], 8
-; ALL-NEXT:    [[S3:%.*]] = shl i16 [[E3]], 12
-; ALL-NEXT:    [[O1:%.*]] = or i16 [[E1]], [[S2]]
-; ALL-NEXT:    [[O2:%.*]] = or i16 [[O1]], [[S3]]
-; ALL-NEXT:    ret i16 [[O2]]
-;
-  %p1 = getelementptr i4, ptr %p, i32 2
-  %p2 = getelementptr i4, ptr %p, i32 3
-  %l1 = load i8, ptr %p
-  %l2 = load i4, ptr %p1
-  %l3 = load i4, ptr %p2
-
-  %e1 = zext i8 %l1 to i16
-  %e2 = zext i4 %l2 to i16
-  %e3 = zext i4 %l3 to i16
-
-  %s2 = shl i16 %e2, 8
-  %s3 = shl i16 %e3, 12
-
-  %o1 = or i16 %e1, %s2
-  %o2 = or i16 %o1, %s3
-  ret i16 %o2
-}
-
-define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size(ptr %p) {
-; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_equal_store_size(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 1
-; ALL-NEXT:    [[L1:%.*]] = load i4, ptr [[P]], align 1
-; ALL-NEXT:    [[L2:%.*]] = load i28, ptr [[P1]], align 4
-; ALL-NEXT:    [[E1:%.*]] = zext i4 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i28 [[L2]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 4
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i4, ptr %p, i32 1
-  %l1 = load i4, ptr %p
-  %l2 = load i28, ptr %p1
-  %e1 = zext i4 %l1 to i32
-  %e2 = zext i28 %l2 to i32
-  %s2 = shl i32 %e2, 4
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size2(ptr %p) {
-; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_equal_store_size2(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 7
-; ALL-NEXT:    [[L1:%.*]] = load i28, ptr [[P]], align 4
-; ALL-NEXT:    [[L2:%.*]] = load i4, ptr [[P1]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i28 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i4 [[L2]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 28
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i4, ptr %p, i32 7
-  %l1 = load i28, ptr %p
-  %l2 = load i4, ptr %p1
-  %e1 = zext i28 %l1 to i32
-  %e2 = zext i4 %l2 to i32
-  %s2 = shl i32 %e2, 28
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size3(ptr %p) {
-; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_equal_store_size3(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i1, ptr [[P:%.*]], i32 23
-; ALL-NEXT:    [[L1:%.*]] = load i23, ptr [[P]], align 4
-; ALL-NEXT:    [[L2:%.*]] = load i9, ptr [[P1]], align 2
-; ALL-NEXT:    [[E1:%.*]] = zext i23 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i9 [[L2]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 24
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i1, ptr %p, i32 23
-  %l1 = load i23, ptr %p
-  %l2 = load i9, ptr %p1
-  %e1 = zext i23 %l1 to i32
-  %e2 = zext i9 %l2 to i32
-  %s2 = shl i32 %e2, 24
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size4(ptr %p) {
-; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_equal_store_size4(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i1, ptr [[P:%.*]], i32 9
-; ALL-NEXT:    [[L1:%.*]] = load i9, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i23, ptr [[P1]], align 4
-; ALL-NEXT:    [[E1:%.*]] = zext i9 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i23 [[L2]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 24
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i1, ptr %p, i32 9
-  %l1 = load i9, ptr %p
-  %l2 = load i23, ptr %p1
-  %e1 = zext i9 %l1 to i32
-  %e2 = zext i23 %l2 to i32
-  %s2 = shl i32 %e2, 24
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i32 @loadCombine_2consecutive_mixsize_not_power_of_two(ptr %p) {
-; LE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two(
-; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
-; LE-NEXT:    ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two(
-; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT:    [[L2:%.*]] = load i24, ptr [[P1]], align 4
-; BE-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT:    [[E2:%.*]] = zext i24 [[L2]] to i32
-; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i8, ptr %p, i32 1
-  %l1 = load i8, ptr %p
-  %l2 = load i24, ptr %p1
-  %e1 = zext i8 %l1 to i32
-  %e2 = zext i24 %l2 to i32
-  %s2 = shl i32 %e2, 8
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i32 @loadCombine_2consecutive_mixsize_not_power_of_two2(ptr %p) {
-; LE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two2(
-; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 4
-; LE-NEXT:    ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_2consecutive_mixsize_not_power_of_two2(
-; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 3
-; BE-NEXT:    [[L1:%.*]] = load i24, ptr [[P]], align 4
-; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT:    [[E1:%.*]] = zext i24 [[L1]] to i32
-; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; BE-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 24
-; BE-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i8, ptr %p, i32 3
-  %l1 = load i24, ptr %p
-  %l2 = load i8, ptr %p1
-  %e1 = zext i24 %l1 to i32
-  %e2 = zext i8 %l2 to i32
-  %s2 = shl i32 %e2, 24
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i32 @loadCombine_2consecutive_sum_size_not_legal(ptr %p) {
-; ALL-LABEL: @loadCombine_2consecutive_sum_size_not_legal(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
-; ALL-NEXT:    [[L1:%.*]] = load i16, ptr [[P]], align 2
-; ALL-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; ALL-NEXT:    [[E1:%.*]] = zext i16 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 16
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i8, ptr %p, i32 2
-  %l1 = load i16, ptr %p
-  %l2 = load i8, ptr %p1
-  %e1 = zext i16 %l1 to i32
-  %e2 = zext i8 %l2 to i32
-  %s2 = shl i32 %e2, 16
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i32 @loadCombine_2consecutive_sum_size_not_legal2(ptr %p) {
-; ALL-LABEL: @loadCombine_2consecutive_sum_size_not_legal2(
-; ALL-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; ALL-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
-; ALL-NEXT:    [[L2:%.*]] = load i16, ptr [[P1]], align 2
-; ALL-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i32
-; ALL-NEXT:    [[E2:%.*]] = zext i16 [[L2]] to i32
-; ALL-NEXT:    [[S2:%.*]] = shl i32 [[E2]], 8
-; ALL-NEXT:    [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; ALL-NEXT:    ret i32 [[O1]]
-;
-  %p1 = getelementptr i8, ptr %p, i32 1
-  %l1 = load i8, ptr %p
-  %l2 = load i16, ptr %p1
-  %e1 = zext i8 %l1 to i32
-  %e2 = zext i16 %l2 to i32
-  %s2 = shl i32 %e2, 8
-  %o1 = or i32 %e1, %s2
-  ret i32 %o1
-}
-
-define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
-; LE-LABEL: @loadCombine_8consecutive_mixsize(
-; LE-NEXT:    [[O3:%.*]] = load i64, ptr [[P:%.*]], align 1
-; LE-NEXT:    ret i64 [[O3]]
-;
-; BE-LABEL: @loadCombine_8consecutive_mixsize(
-; BE-NEXT:    [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
-; BE-NEXT:    [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2
-; BE-NEXT:    [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
-; BE-NEXT:    [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT:    [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT:    [[L3:%.*]] = load i16, ptr [[P2]], align 2
-; BE-NEXT:    [[L4:%.*]] = load i32, ptr [[P3]], align 4
-; BE-NEXT:    [[E1:%.*]] = zext i8 [[L1]] to i64
-; BE-NEXT:    [[E2:%.*]] = zext i8 [[L2]] to i64
-; BE-NEXT:    [[E3:%.*]] = zext i16 [[L3]] to i64
-; BE-NEXT:    [[E4:%.*]] = zext i32 [[L4]] to i64
-; BE-NEXT:    [[S2:%.*]] = shl i64 [[E2]], 8
-; BE-NEXT:    [[S3:%.*]] = shl i64 [[E3]], 16
-; BE-NEXT:    [[S4:%.*]] = shl i64 [[E4]], 32
-; BE-NEXT:    [[O1:%.*]] = or i64 [[E1]], [[S2]]
-; BE-NEXT:    [[O2:%.*]] = or i64 [[O1]], [[S3]]
-; BE-NEXT:    [[O3:%.*]] = or i64 [[O2]], [[S4]]
-; BE-NEXT:    ret i64 [[O3]]
-;
-  %p1 = getelementptr i8, ptr %p, i64 1
-  %p2 = getelementptr i8, ptr %p, i64 2
-  %p3 = getelementptr i8, ptr %p, i64 4
-  %l1 = load i8, ptr %p
-  %l2 = load i8, ptr %p1
-  %l3 = load i16, ptr %p2
-  %l4 = load i32, ptr %p3
-
-  %e1 = zext i8 %l1 to i64
-  %e2 = zext i8 %l2 to i64
-  %e3 = zext i16 %l3 to i64
-  %e4 = zext i32 %l4 to i64
-
-  %s2 = shl i64 %e2, 8
-  %s3 = shl i64 %e3, 16
-  %s4 = shl i64 %e4, 32
-
-  %o1 = or i64 %e1, %s2
-  %o2 = or i64 %o1, %s3
-  %o3 = or i64 %o2, %s4
-  ret i64 %o3
-}
-
 define i32 @loadCombine_4consecutive_lower_index_comes_before(ptr %p) {
 ; LE-LABEL: @loadCombine_4consecutive_lower_index_comes_before(
 ; LE-NEXT:    [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1