Move CPUInfo to header and add CPUModel struct

Author: wangpc-pp

llvm/include/llvm/TargetParser/RISCVTargetParser.h

@@ -32,6 +32,21 @@ struct RISCVExtensionBitmask {
 };
 } // namespace RISCVExtensionBitmaskTable
 
+struct CPUModel {
+  uint32_t MVendorID;
+  uint64_t MArchID;
+  uint64_t MImpID;
+};
+
+struct CPUInfo {
+  StringLiteral Name;
+  StringLiteral DefaultMarch;
+  bool FastScalarUnalignedAccess;
+  bool FastVectorUnalignedAccess;
+  CPUModel CPUModel;
+  bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
+};
+
 // We use 64 bits as the known part in the scalable vector types.
 static constexpr unsigned RVVBitsPerBlock = 64;
 

llvm/lib/TargetParser/RISCVTargetParser.cpp

@@ -27,17 +27,6 @@ enum CPUKind : unsigned {
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };
 
-struct CPUInfo {
-  StringLiteral Name;
-  StringLiteral DefaultMarch;
-  bool FastScalarUnalignedAccess;
-  bool FastVectorUnalignedAccess;
-  uint32_t MVendorID;
-  uint64_t MArchID;
-  uint64_t MImpID;
-  bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
-};
-
 constexpr CPUInfo RISCVCPUInfo[] = {
 #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN,                   \
              FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)                  \
@@ -46,9 +35,7 @@ constexpr CPUInfo RISCVCPUInfo[] = {
       DEFAULT_MARCH,                                                           \
       FAST_SCALAR_UNALIGN,                                                     \
       FAST_VECTOR_UNALIGN,                                                     \
-      MVENDORID,                                                               \
-      MARCHID,                                                                 \
-      MIMPID,                                                                  \
+      {MVENDORID, MARCHID, MIMPID},                                            \
   },
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };