fix the comments

LiqinWeng · LiqinWeng · commit 1588e926e5df · 2024-12-01T13:23:34.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1462,7 +1462,7 @@ RISCVTTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
     return ExtraCost + getRISCVInstructionCost(Opcodes, LT.second, CostKind);
   }
 
-  // IR Reduction is composed by two vmv and one rvv reduction instruction.
+  // IR Reduction is composed by one rvv reduction instruction and vmv
   unsigned SplitOp;
   SmallVector<unsigned, 3> Opcodes;
   switch (IID) {
@@ -1554,7 +1554,9 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
     }
   }
 
-  // IR Reduction is composed by two vmv and one rvv reduction instruction.
+  // IR Reduction of or/and is composed by one vmv and one rvv reduction
+  // instruction, and others is composed by two vmv and one rvv reduction
+  // instruction
   unsigned SplitOp;
   switch (ISD) {
   case ISD::ADD:

Original file line number	Diff line number	Diff line change
`@@ -1462,7 +1462,7 @@ RISCVTTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,`
`1462`	`1462`	`return ExtraCost + getRISCVInstructionCost(Opcodes, LT.second, CostKind);`
`1463`	`1463`	`}`
`1464`	`1464`
`1465`		`- // IR Reduction is composed by two vmv and one rvv reduction instruction.`
	`1465`	`+ // IR Reduction is composed by one rvv reduction instruction and vmv`
`1466`	`1466`	`unsigned SplitOp;`
`1467`	`1467`	`SmallVector<unsigned, 3> Opcodes;`
`1468`	`1468`	`switch (IID) {`
`@@ -1554,7 +1554,9 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,`
`1554`	`1554`	`}`
`1555`	`1555`	`}`
`1556`	`1556`
`1557`		`- // IR Reduction is composed by two vmv and one rvv reduction instruction.`
	`1557`	`+ // IR Reduction of or/and is composed by one vmv and one rvv reduction`
	`1558`	`+ // instruction, and others is composed by two vmv and one rvv reduction`
	`1559`	`+ // instruction`
`1558`	`1560`	`unsigned SplitOp;`
`1559`	`1561`	`switch (ISD) {`
`1560`	`1562`	`case ISD::ADD:`