[CodeGen] Port MachineUniformityAnalysis to new pass manager (#137578)

- Add new pass manager version of `MachineUniformityAnalysis `.
- Query `TargetTransformInfo` in new pass manager version.
- Use `printAsOperand` when printing machine function name

Author: paperchalice

llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h

@@ -17,6 +17,7 @@
 #include "llvm/ADT/GenericUniformityInfo.h"
 #include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachinePassManager.h"
 #include "llvm/CodeGen/MachineSSAContext.h"
 
 namespace llvm {
@@ -51,6 +52,27 @@ class MachineUniformityAnalysisPass : public MachineFunctionPass {
   // TODO: verify analysis
 };
 
+class MachineUniformityAnalysis
+    : public AnalysisInfoMixin<MachineUniformityAnalysis> {
+  friend AnalysisInfoMixin<MachineUniformityAnalysis>;
+  static AnalysisKey Key;
+
+public:
+  using Result = MachineUniformityInfo;
+  Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+class MachineUniformityPrinterPass
+    : public PassInfoMixin<MachineUniformityAnalysis> {
+  raw_ostream &OS;
+
+public:
+  explicit MachineUniformityPrinterPass(raw_ostream &OS) : OS(OS) {}
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
+};
+
 } // namespace llvm
 
 #endif // LLVM_CODEGEN_MACHINEUNIFORMITYANALYSIS_H

llvm/include/llvm/Passes/MachinePassRegistry.def

@@ -114,6 +114,7 @@ MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
 MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
                           MachinePostDominatorTreeAnalysis())
 MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-uniformity", MachineUniformityAnalysis())
 MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
 MACHINE_FUNCTION_ANALYSIS("regalloc-evict", RegAllocEvictionAdvisorAnalysis())
 MACHINE_FUNCTION_ANALYSIS("regalloc-priority", RegAllocPriorityAdvisorAnalysis())
@@ -178,6 +179,8 @@ MACHINE_FUNCTION_PASS("print<machine-dom-tree>",
 MACHINE_FUNCTION_PASS("print<machine-loops>", MachineLoopPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<machine-post-dom-tree>",
                       MachinePostDominatorTreePrinterPass(errs()))
+MACHINE_FUNCTION_PASS("print<machine-uniformity>",
+                      MachineUniformityPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<virtregmap>", VirtRegMapPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("prolog-epilog", PrologEpilogInserterPass())
@@ -303,11 +306,9 @@ DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass)
 DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass)
 DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter)
 DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
-DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
 DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
 DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
 DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
-DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", MachineUniformityInfoPrinterPass)
 DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
 DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass)
 DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)

llvm/lib/CodeGen/MachineUniformityAnalysis.cpp

@@ -8,6 +8,7 @@
 
 #include "llvm/CodeGen/MachineUniformityAnalysis.h"
 #include "llvm/ADT/GenericUniformityImpl.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -177,6 +178,32 @@ class MachineUniformityInfoPrinterPass : public MachineFunctionPass {
 
 } // namespace
 
+AnalysisKey MachineUniformityAnalysis::Key;
+
+MachineUniformityAnalysis::Result
+MachineUniformityAnalysis::run(MachineFunction &MF,
+                               MachineFunctionAnalysisManager &MFAM) {
+  auto &DomTree = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+  auto &CI = MFAM.getResult<MachineCycleAnalysis>(MF);
+  auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+                  .getManager();
+  auto &F = MF.getFunction();
+  auto &TTI = FAM.getResult<TargetIRAnalysis>(F);
+  return computeMachineUniformityInfo(MF, CI, DomTree,
+                                      TTI.hasBranchDivergence(&F));
+}
+
+PreservedAnalyses
+MachineUniformityPrinterPass::run(MachineFunction &MF,
+                                  MachineFunctionAnalysisManager &MFAM) {
+  auto &MUI = MFAM.getResult<MachineUniformityAnalysis>(MF);
+  OS << "MachineUniformityInfo for function: ";
+  MF.getFunction().printAsOperand(OS, /*PrintType=*/false);
+  OS << '\n';
+  MUI.print(OS);
+  return PreservedAnalyses::all();
+}
+
 char MachineUniformityAnalysisPass::ID = 0;
 
 MachineUniformityAnalysisPass::MachineUniformityAnalysisPass()
@@ -209,8 +236,9 @@ bool MachineUniformityAnalysisPass::runOnMachineFunction(MachineFunction &MF) {
 
 void MachineUniformityAnalysisPass::print(raw_ostream &OS,
                                           const Module *) const {
-  OS << "MachineUniformityInfo for function: " << UI.getFunction().getName()
-     << "\n";
+  OS << "MachineUniformityInfo for function: ";
+  UI.getFunction().getFunction().printAsOperand(OS, /*PrintType=*/false);
+  OS << '\n';
   UI.print(OS);
 }
 

llvm/lib/Passes/PassBuilder.cpp

@@ -133,6 +133,7 @@
 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/MachineSink.h"
 #include "llvm/CodeGen/MachineTraceMetrics.h"
+#include "llvm/CodeGen/MachineUniformityAnalysis.h"
 #include "llvm/CodeGen/MachineVerifier.h"
 #include "llvm/CodeGen/OptimizePHIs.h"
 #include "llvm/CodeGen/PEI.h"

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir

@@ -1,10 +1,11 @@
 # NOTE: This file is Generic MIR translation of test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll test file
 # RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
 ---
 name:            readfirstlane
 body:             |
   bb.1:
-    ; CHECK-LABEL: MachineUniformityInfo for function: readfirstlane
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @readfirstlane
     ; CHECK: DIVERGENT: %{{[0-9]+}}
     ; CHECK-SAME:llvm.amdgcn.workitem.id.x
     ; CHECK-NOT: DIVERGENT: {{.*}}llvm.amdgcn.readfirstlane
@@ -19,7 +20,7 @@ name:            icmp
 body:             |
   bb.1:
     liveins: $sgpr4_sgpr5
-    ; CHECK-LABEL: MachineUniformityInfo for function: icmp
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @icmp
     ; CHECK-NEXT: ALL VALUES UNIFORM
 
     %3:_(p4) = COPY $sgpr4_sgpr5
@@ -39,7 +40,7 @@ name:            fcmp
 body:             |
   bb.1:
     liveins: $sgpr4_sgpr5
-    ; CHECK-LABEL: MachineUniformityInfo for function: fcmp
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @fcmp
     ; CHECK-NEXT: ALL VALUES UNIFORM
 
     %3:_(p4) = COPY $sgpr4_sgpr5
@@ -62,7 +63,7 @@ name:            ballot
 body:             |
   bb.1:
     liveins: $sgpr4_sgpr5
-    ; CHECK-LABEL: MachineUniformityInfo for function: ballot
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @ballot
     ; CHECK-NEXT: ALL VALUES UNIFORM
 
     %2:_(p4) = COPY $sgpr4_sgpr5
@@ -85,7 +86,7 @@ registers:
 body:             |
   bb.0:
     liveins: $vgpr0
-    ; CHECK-LABEL: MachineUniformityInfo for function: asm_sgpr
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @asm_sgpr
     ; CHECK-NOT: DIVERGENT: %1
 
     %0:_(s32) = COPY $vgpr0
@@ -112,7 +113,7 @@ frameInfo:
 body:             |
   bb.0:
     liveins: $vgpr0
-    ; CHECK-LABEL: MachineUniformityInfo for function: asm_mixed_sgpr_vgpr
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @asm_mixed_sgpr_vgpr
     ; CHECK: DIVERGENT: %0:
     ; CHECK: DIVERGENT: %3:
     ; CHECK-NOT: DIVERGENT: %1:

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir

@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
 
 # readlane, readfirstlane is always uniform
 
@@ -8,7 +9,7 @@ machineFunctionInfo:
   isEntryFunction: true
 body:             |
   bb.0:
-    ; CHECK-LABEL: MachineUniformityInfo for function: readlane
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @readlane
     ; CHECK-NEXT: ALL VALUES UNIFORM
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
@@ -26,7 +27,7 @@ machineFunctionInfo:
   isEntryFunction: true
 body:             |
   bb.0:
-    ; CHECK-LABEL: MachineUniformityInfo for function: readlane2
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @readlane2
     ; CHECK-NEXT: ALL VALUES UNIFORM
     %0:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
@@ -47,7 +48,7 @@ machineFunctionInfo:
   isEntryFunction: true
 body:             |
   bb.0:
-    ; CHECK-LABEL: MachineUniformityInfo for function: sgprcopy
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @sgprcopy
     ; CHECK-NEXT: ALL VALUES UNIFORM
     liveins: $sgpr0,$sgpr1,$vgpr0
     %0:sgpr_32 = COPY $sgpr0

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir

@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
 
 ---
 name:            test1

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir

@@ -1,11 +1,12 @@
 # RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
 
 ---
 name:            test1
 tracksRegLiveness: true
 body:             |
   bb.0:
-    ; CHECK-LABEL: MachineUniformityInfo for function: test1
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @test1
     %2:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %0:vgpr_32 = IMPLICIT_DEF
@@ -25,7 +26,7 @@ name:            test2
 tracksRegLiveness: true
 body:             |
   bb.0:
-    ; CHECK-LABEL: MachineUniformityInfo for function: test2
+    ; CHECK-LABEL: MachineUniformityInfo for function:  @test2
     %3:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
@@ -48,7 +49,7 @@ name:            atomic_inc
 tracksRegLiveness: true
 body:             |
   bb.0:
-  ; CHECK-LABEL: MachineUniformityInfo for function: atomic_inc
+  ; CHECK-LABEL: MachineUniformityInfo for function:  @atomic_inc
     %2:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %0:vgpr_32 = IMPLICIT_DEF
@@ -65,7 +66,7 @@ name:            atomic_inc_64
 tracksRegLiveness: true
 body:             |
   bb.0:
-  ; CHECK-LABEL: MachineUniformityInfo for function: atomic_inc_64
+  ; CHECK-LABEL: MachineUniformityInfo for function:  @atomic_inc_64
     %3:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
@@ -88,7 +89,7 @@ name:            atomic_dec
 tracksRegLiveness: true
 body:             |
   bb.0:
-  ; CHECK-LABEL: MachineUniformityInfo for function: atomic_dec
+  ; CHECK-LABEL: MachineUniformityInfo for function:  @atomic_dec
     %2:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF
     %0:vgpr_32 = IMPLICIT_DEF
@@ -106,7 +107,7 @@ name:            atomic_dec_64
 tracksRegLiveness: true
 body:             |
   bb.0:
-  ; CHECK-LABEL: MachineUniformityInfo for function: atomic_dec_64
+  ; CHECK-LABEL: MachineUniformityInfo for function:  @atomic_dec_64
     %3:vgpr_32 = IMPLICIT_DEF
     %2:vgpr_32 = IMPLICIT_DEF
     %1:vgpr_32 = IMPLICIT_DEF

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir

@@ -1,9 +1,10 @@
 # RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
 
 ---
 name:            f1
 body:             |
-  ; CHECK-LABEL: MachineUniformityInfo for function: f1
+  ; CHECK-LABEL: MachineUniformityInfo for function:  @f1
   bb.0:
     successors: %bb.1, %bb.2
 
@@ -23,7 +24,7 @@ body:             |
 ---
 name:            f2
 body:             |
-  ; CHECK-LABEL: MachineUniformityInfo for function: f2
+  ; CHECK-LABEL: MachineUniformityInfo for function:  @f2
   bb.0:
     successors: %bb.1, %bb.2
 

llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir

@@ -1,5 +1,6 @@
 # RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# CHECK-LABEL: MachineUniformityInfo for function: hidden_diverge
+# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# CHECK-LABEL: MachineUniformityInfo for function:  @hidden_diverge
 # CHECK-LABEL: BLOCK bb.0
 # CHECK:     DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
 # CHECK:     DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1) = G_ICMP intpred(slt)