@@ -1266,98 +1266,98 @@ void test_builtin_elementwise_fshl(long long int i1, long long int i2,
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u4 tmp_vu_r = __builtin_elementwise_fshr (vu1 , vu2 , vu3 );
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}
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- void test_builtin_elementwise_ctlz (si8 vs1 , si8 vs2 , u4 vu1 ,
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+ void test_builtin_elementwise_clzg (si8 vs1 , si8 vs2 , u4 vu1 ,
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long long int lli , short si ,
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_BitInt (31 ) bi , int i ,
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char ci ) {
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// CHECK: [[V8S1:%.+]] = load <8 x i16>, ptr %vs1.addr
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// CHECK-NEXT: call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[V8S1]], i1 true)
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- vs1 = __builtin_elementwise_ctlz (vs1 );
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+ vs1 = __builtin_elementwise_clzg (vs1 );
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// CHECK: [[V8S1:%.+]] = load <8 x i16>, ptr %vs1.addr
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// CHECK-NEXT: [[CLZ:%.+]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[V8S1]], i1 true)
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// CHECK-NEXT: [[ISZERO:%.+]] = icmp eq <8 x i16> [[V8S1]], zeroinitializer
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// CHECK-NEXT: [[V8S2:%.+]] = load <8 x i16>, ptr %vs2.addr
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// select <8 x i1> [[ISZERO]], <8 x i16> [[CLZ]], <8 x i16> [[V8S2]]
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- vs1 = __builtin_elementwise_ctlz (vs1 , vs2 );
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+ vs1 = __builtin_elementwise_clzg (vs1 , vs2 );
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// CHECK: [[V4U1:%.+]] = load <4 x i32>, ptr %vu1.addr
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// CHECK-NEXT: call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[V4U1]], i1 true)
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- vu1 = __builtin_elementwise_ctlz (vu1 );
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+ vu1 = __builtin_elementwise_clzg (vu1 );
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// CHECK: [[LLI:%.+]] = load i64, ptr %lli.addr
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// CHECK-NEXT: call i64 @llvm.ctlz.i64(i64 [[LLI]], i1 true)
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- lli = __builtin_elementwise_ctlz (lli );
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+ lli = __builtin_elementwise_clzg (lli );
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// CHECK: [[SI:%.+]] = load i16, ptr %si.addr
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// CHECK-NEXT: call i16 @llvm.ctlz.i16(i16 [[SI]], i1 true)
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- si = __builtin_elementwise_ctlz (si );
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+ si = __builtin_elementwise_clzg (si );
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// CHECK: [[BI1:%.+]] = load i32, ptr %bi.addr
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// CHECK-NEXT: [[BI2:%.+]] = trunc i32 [[BI1]] to i31
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// CHECK-NEXT: call i31 @llvm.ctlz.i31(i31 [[BI2]], i1 true)
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- bi = __builtin_elementwise_ctlz (bi );
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+ bi = __builtin_elementwise_clzg (bi );
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// CHECK: [[BI1:%.+]] = load i32, ptr %bi.addr
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// CHECK-NEXT: [[BI2:%.+]] = trunc i32 [[BI1]] to i31
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// CHECK-NEXT: [[CLZ:%.+]] = call i31 @llvm.ctlz.i31(i31 [[BI2]], i1 true)
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// CHECK-NEXT: [[ISZERO:%.+]] = icmp eq i31 [[BI2]], 0
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// CHECK-NEXT: select i1 [[ISZERO]], i31 1, i31 [[CLZ]]
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- bi = __builtin_elementwise_ctlz (bi , (_BitInt (31 ))1 );
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+ bi = __builtin_elementwise_clzg (bi , (_BitInt (31 ))1 );
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// CHECK: [[I:%.+]] = load i32, ptr %i.addr
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// CHECK-NEXT: call i32 @llvm.ctlz.i32(i32 [[I]], i1 true)
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- i = __builtin_elementwise_ctlz (i );
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+ i = __builtin_elementwise_clzg (i );
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// CHECK: [[CI:%.+]] = load i8, ptr %ci.addr
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// CHECK-NEXT: call i8 @llvm.ctlz.i8(i8 [[CI]], i1 true)
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- ci = __builtin_elementwise_ctlz (ci );
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+ ci = __builtin_elementwise_clzg (ci );
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}
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- void test_builtin_elementwise_cttz (si8 vs1 , si8 vs2 , u4 vu1 ,
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+ void test_builtin_elementwise_ctzg (si8 vs1 , si8 vs2 , u4 vu1 ,
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long long int lli , short si ,
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_BitInt (31 ) bi , int i ,
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char ci ) {
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// CHECK: [[V8S1:%.+]] = load <8 x i16>, ptr %vs1.addr
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// CHECK-NEXT: call <8 x i16> @llvm.cttz.v8i16(<8 x i16> [[V8S1]], i1 true)
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- vs1 = __builtin_elementwise_cttz (vs1 );
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+ vs1 = __builtin_elementwise_ctzg (vs1 );
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// CHECK: [[V8S1:%.+]] = load <8 x i16>, ptr %vs1.addr
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// CHECK-NEXT: [[ctz:%.+]] = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> [[V8S1]], i1 true)
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// CHECK-NEXT: [[ISZERO:%.+]] = icmp eq <8 x i16> [[V8S1]], zeroinitializer
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// CHECK-NEXT: [[V8S2:%.+]] = load <8 x i16>, ptr %vs2.addr
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// select <8 x i1> [[ISZERO]], <8 x i16> [[ctz]], <8 x i16> [[V8S2]]
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- vs1 = __builtin_elementwise_cttz (vs1 , vs2 );
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+ vs1 = __builtin_elementwise_ctzg (vs1 , vs2 );
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// CHECK: [[V4U1:%.+]] = load <4 x i32>, ptr %vu1.addr
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// CHECK-NEXT: call <4 x i32> @llvm.cttz.v4i32(<4 x i32> [[V4U1]], i1 true)
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- vu1 = __builtin_elementwise_cttz (vu1 );
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+ vu1 = __builtin_elementwise_ctzg (vu1 );
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// CHECK: [[LLI:%.+]] = load i64, ptr %lli.addr
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// CHECK-NEXT: call i64 @llvm.cttz.i64(i64 [[LLI]], i1 true)
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- lli = __builtin_elementwise_cttz (lli );
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+ lli = __builtin_elementwise_ctzg (lli );
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// CHECK: [[SI:%.+]] = load i16, ptr %si.addr
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// CHECK-NEXT: call i16 @llvm.cttz.i16(i16 [[SI]], i1 true)
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- si = __builtin_elementwise_cttz (si );
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+ si = __builtin_elementwise_ctzg (si );
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// CHECK: [[BI1:%.+]] = load i32, ptr %bi.addr
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// CHECK-NEXT: [[BI2:%.+]] = trunc i32 [[BI1]] to i31
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// CHECK-NEXT: call i31 @llvm.cttz.i31(i31 [[BI2]], i1 true)
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- bi = __builtin_elementwise_cttz (bi );
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+ bi = __builtin_elementwise_ctzg (bi );
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// CHECK: [[BI1:%.+]] = load i32, ptr %bi.addr
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// CHECK-NEXT: [[BI2:%.+]] = trunc i32 [[BI1]] to i31
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// CHECK-NEXT: [[ctz:%.+]] = call i31 @llvm.cttz.i31(i31 [[BI2]], i1 true)
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// CHECK-NEXT: [[ISZERO:%.+]] = icmp eq i31 [[BI2]], 0
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// CHECK-NEXT: select i1 [[ISZERO]], i31 1, i31 [[ctz]]
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- bi = __builtin_elementwise_cttz (bi , (_BitInt (31 ))1 );
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+ bi = __builtin_elementwise_ctzg (bi , (_BitInt (31 ))1 );
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// CHECK: [[I:%.+]] = load i32, ptr %i.addr
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// CHECK-NEXT: call i32 @llvm.cttz.i32(i32 [[I]], i1 true)
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- i = __builtin_elementwise_cttz (i );
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+ i = __builtin_elementwise_ctzg (i );
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// CHECK: [[CI:%.+]] = load i8, ptr %ci.addr
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// CHECK-NEXT: call i8 @llvm.cttz.i8(i8 [[CI]], i1 true)
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- ci = __builtin_elementwise_cttz (ci );
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+ ci = __builtin_elementwise_ctzg (ci );
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}
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