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[RISCV] Add software pipeliner support
This patch adds basic support of `MachinePipeliner` and disable it by default. The functionality should be OK and all llvm-test-suite tests have passed.
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4136,3 +4136,84 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
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return false;
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return LHS.getImm() <= RHS.getImm();
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}
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namespace {
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class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
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const MachineInstr *LHS;
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const MachineInstr *RHS;
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SmallVector<MachineOperand, 4> Cond;
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public:
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RISCVPipelinerLoopInfo(const MachineInstr *LHS, const MachineInstr *RHS,
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const SmallVectorImpl<MachineOperand> &Cond)
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: LHS(LHS), RHS(RHS), Cond(Cond.begin(), Cond.end()) {}
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bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
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// Make the instructions for loop control be placed in stage 0.
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// The predecessors of PredBranch are considered by the caller.
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if (LHS && MI == LHS)
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return true;
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if (RHS && MI == RHS)
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return true;
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return false;
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}
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std::optional<bool> createTripCountGreaterCondition(
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int TC, MachineBasicBlock &MBB,
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SmallVectorImpl<MachineOperand> &CondParam) override {
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// A branch instruction will be inserted as "if (Cond) goto epilogue".
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// Cond is normalized for such use.
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// The predecessors of the branch are assumed to have already been inserted.
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CondParam = Cond;
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return {};
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}
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void setPreheader(MachineBasicBlock *NewPreheader) override {}
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void adjustTripCount(int TripCountAdjust) override {}
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void disposed() override {}
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};
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} // namespace
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std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
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RISCVInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
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MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
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SmallVector<MachineOperand, 4> Cond;
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if (analyzeBranch(*LoopBB, TBB, FBB, Cond, /*AllowModify=*/false))
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return nullptr;
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// Infinite loops are not supported
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if (TBB == LoopBB && FBB == LoopBB)
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return nullptr;
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// Must be conditional branch
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if (FBB == nullptr)
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return nullptr;
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assert((TBB == LoopBB || FBB == LoopBB) &&
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"The Loop must be a single-basic-block loop");
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// Normalization for createTripCountGreaterCondition()
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if (TBB == LoopBB)
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reverseBranchCondition(Cond);
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const MachineRegisterInfo &MRI = LoopBB->getParent()->getRegInfo();
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auto FindRegDef = [&MRI](MachineOperand &Op) -> const MachineInstr * {
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if (!Op.isReg())
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return nullptr;
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Register Reg = Op.getReg();
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if (!Reg.isVirtual())
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return nullptr;
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return MRI.getVRegDef(Reg);
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};
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const MachineInstr *LHS = FindRegDef(Cond[1]);
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const MachineInstr *RHS = FindRegDef(Cond[2]);
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if (LHS && LHS->isPHI())
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return nullptr;
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if (RHS && RHS->isPHI())
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return nullptr;
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return std::make_unique<RISCVPipelinerLoopInfo>(LHS, RHS, Cond);
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}

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -293,6 +293,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
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unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
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std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
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analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
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protected:
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const RISCVSubtarget &STI;
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‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,10 @@ bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
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bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
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bool RISCVSubtarget::enableMachinePipeliner() const {
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return getSchedModel().hasInstrSchedModel();
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}
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void RISCVSubtarget::getPostRAMutations(
190194
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
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Mutations.push_back(createMacroFusionDAGMutation(getMacroFusions()));

‎llvm/lib/Target/RISCV/RISCVSubtarget.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -304,6 +304,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
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void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
305305
&Mutations) const override;
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bool enableMachinePipeliner() const override;
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bool useDFAforSMS() const override { return false; }
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bool useAA() const override;
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unsigned getCacheLineSize() const override {

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,11 @@ static cl::opt<bool>
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cl::desc("Enable the RISC-V VL Optimizer pass"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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EnableMachinePipeliner("riscv-enable-pipeliner",
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cl::desc("Enable Machine Pipeliner for RISC-V"),
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cl::init(false), cl::Hidden);
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
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RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@@ -600,6 +605,9 @@ void RISCVPassConfig::addPreRegAlloc() {
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addPass(createRISCVInsertReadWriteCSRPass());
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addPass(createRISCVInsertWriteVXRMPass());
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addPass(createRISCVLandingPadSetupPass());
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if (TM->getOptLevel() != CodeGenOptLevel::None && EnableMachinePipeliner)
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addPass(&MachinePipelinerID);
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}
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void RISCVPassConfig::addFastRegAlloc() {

‎llvm/test/CodeGen/RISCV/machine-pipeliner.ll‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv64 -mcpu=sifive-p670 -O3 -verify-machineinstrs -riscv-enable-pipeliner=false < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK-NOT-PIPELINED
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; RUN: llc -mtriple=riscv64 -mcpu=sifive-p670 -O3 -verify-machineinstrs -riscv-enable-pipeliner=true < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK-PIPELINED
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define void @test_1(ptr noalias %in, ptr noalias %out, i32 signext %cnt) "no-builtins" {
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; CHECK-NOT-PIPELINED-LABEL: test_1:
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; CHECK-NOT-PIPELINED: # %bb.0: # %entry
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; CHECK-NOT-PIPELINED-NEXT: blez a2, .LBB0_3
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; CHECK-NOT-PIPELINED-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NOT-PIPELINED-NEXT: addi a2, a2, -1
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; CHECK-NOT-PIPELINED-NEXT: sh2add.uw a2, a2, a1
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; CHECK-NOT-PIPELINED-NEXT: addi a2, a2, 4
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; CHECK-NOT-PIPELINED-NEXT: .LBB0_2: # %for.body
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; CHECK-NOT-PIPELINED-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NOT-PIPELINED-NEXT: lw a3, 0(a1)
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; CHECK-NOT-PIPELINED-NEXT: addi a1, a1, 4
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; CHECK-NOT-PIPELINED-NEXT: sw a3, 0(a0)
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; CHECK-NOT-PIPELINED-NEXT: addi a0, a0, 4
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; CHECK-NOT-PIPELINED-NEXT: bne a1, a2, .LBB0_2
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; CHECK-NOT-PIPELINED-NEXT: .LBB0_3: # %for.end
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; CHECK-NOT-PIPELINED-NEXT: ret
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;
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; CHECK-PIPELINED-LABEL: test_1:
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; CHECK-PIPELINED: # %bb.0: # %entry
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; CHECK-PIPELINED-NEXT: blez a2, .LBB0_6
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; CHECK-PIPELINED-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-PIPELINED-NEXT: lw a3, 0(a1)
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; CHECK-PIPELINED-NEXT: addi a2, a2, -1
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; CHECK-PIPELINED-NEXT: addi a4, a0, 4
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; CHECK-PIPELINED-NEXT: sh2add.uw a6, a2, a1
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; CHECK-PIPELINED-NEXT: addi a1, a1, 4
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; CHECK-PIPELINED-NEXT: addi a6, a6, 4
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; CHECK-PIPELINED-NEXT: beq a1, a6, .LBB0_5
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; CHECK-PIPELINED-NEXT: # %bb.2: # %for.body
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; CHECK-PIPELINED-NEXT: lw a5, 0(a1)
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; CHECK-PIPELINED-NEXT: addi a2, a4, 4
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; CHECK-PIPELINED-NEXT: addi a1, a1, 4
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; CHECK-PIPELINED-NEXT: beq a1, a6, .LBB0_4
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; CHECK-PIPELINED-NEXT: .LBB0_3: # %for.body
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; CHECK-PIPELINED-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-PIPELINED-NEXT: sw a3, 0(a0)
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; CHECK-PIPELINED-NEXT: mv a3, a5
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; CHECK-PIPELINED-NEXT: lw a5, 0(a1)
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; CHECK-PIPELINED-NEXT: mv a0, a4
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; CHECK-PIPELINED-NEXT: mv a4, a2
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; CHECK-PIPELINED-NEXT: addi a2, a2, 4
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; CHECK-PIPELINED-NEXT: addi a1, a1, 4
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; CHECK-PIPELINED-NEXT: bne a1, a6, .LBB0_3
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; CHECK-PIPELINED-NEXT: .LBB0_4:
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; CHECK-PIPELINED-NEXT: sw a3, 0(a0)
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; CHECK-PIPELINED-NEXT: mv a0, a4
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; CHECK-PIPELINED-NEXT: mv a3, a5
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; CHECK-PIPELINED-NEXT: .LBB0_5:
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; CHECK-PIPELINED-NEXT: sw a3, 0(a0)
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; CHECK-PIPELINED-NEXT: .LBB0_6: # %for.end
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; CHECK-PIPELINED-NEXT: ret
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entry:
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%cmp5 = icmp sgt i32 %cnt, 0
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br i1 %cmp5, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%in.addr.07 = phi ptr [ %incdec.ptr, %for.body ], [ %in, %entry ]
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%out.addr.06 = phi ptr [ %incdec.ptr1, %for.body ], [ %out, %entry ]
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%0 = load i32, ptr %out.addr.06, align 4
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store i32 %0, ptr %in.addr.07, align 4
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%incdec.ptr = getelementptr inbounds i8, ptr %in.addr.07, i64 4
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%incdec.ptr1 = getelementptr inbounds i8, ptr %out.addr.06, i64 4
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%inc = add nuw nsw i32 %i.08, 1
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%exitcond.not = icmp eq i32 %inc, %cnt
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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