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Merge branch 'main' into users/rampitec/07-30-_amdgpu_add_v_ashr_pk_i8_i32_and_v_ashr_pk_u8_i32_on_gfx1250
2 parents af80984 + 8377f90 commit 15cf429

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-4
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4 files changed

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compiler-rt/lib/memprof/memprof_interface_internal.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,9 +35,15 @@ SANITIZER_INTERFACE_ATTRIBUTE void __memprof_version_mismatch_check_v1();
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SANITIZER_INTERFACE_ATTRIBUTE
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void __memprof_record_access(void const volatile *addr);
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SANITIZER_INTERFACE_ATTRIBUTE
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void __memprof_record_access_hist(void const volatile *addr);
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SANITIZER_INTERFACE_ATTRIBUTE
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void __memprof_record_access_range(void const volatile *addr, uptr size);
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SANITIZER_INTERFACE_ATTRIBUTE
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void __memprof_record_access_range_hist(void const volatile *addr, uptr size);
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SANITIZER_INTERFACE_ATTRIBUTE void __memprof_print_accumulated_stats();
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SANITIZER_INTERFACE_ATTRIBUTE SANITIZER_WEAK_ATTRIBUTE extern char
@@ -51,6 +57,10 @@ extern uptr __memprof_shadow_memory_dynamic_address;
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SANITIZER_INTERFACE_ATTRIBUTE SANITIZER_WEAK_ATTRIBUTE extern char
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__memprof_profile_filename[1];
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SANITIZER_INTERFACE_ATTRIBUTE SANITIZER_WEAK_ATTRIBUTE extern bool
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__memprof_histogram;
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SANITIZER_INTERFACE_ATTRIBUTE int __memprof_profile_dump();
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SANITIZER_INTERFACE_ATTRIBUTE void __memprof_profile_reset();
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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
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// Test the histogram support in memprof using the text format output.
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// Shadow memory counters per object are limited to 8b. In memory counters
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// aggregating counts across multiple objects are 64b.
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// RUN: %clangxx_memprof -O0 -mllvm -memprof-histogram -mllvm -memprof-use-callbacks=true %s -o %t
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// RUN: %env_memprof_opts=print_text=1:histogram=1:log_path=stdout %run %t 2>&1 | FileCheck %s
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#include <stdio.h>
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#include <stdlib.h>
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int main() {
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// Allocate memory that will create a histogram
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char *buffer = (char *)malloc(1024);
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if (!buffer)
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return 1;
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for (int i = 0; i < 10; ++i) {
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// Access every 8th byte (since shadow granularity is 8b.
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buffer[i * 8] = 'A';
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}
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for (int j = 0; j < 200; ++j) {
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buffer[8] = 'B'; // Count = previous count + 200
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}
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for (int j = 0; j < 400; ++j) {
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buffer[16] = 'B'; // Count is saturated at 255
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}
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// Free the memory to trigger MIB creation with histogram
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free(buffer);
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printf("Test completed successfully\n");
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return 0;
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}
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// CHECK: AccessCountHistogram[128]: 1 201 255 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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// CHECK: Test completed successfully

libc/src/math/generic/atan2l.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ namespace LIBC_NAMESPACE_DECL {
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LLVM_LIBC_FUNCTION(long double, atan2l, (long double y, long double x)) {
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#if defined(LIBC_TYPES_LONG_DOUBLE_IS_FLOAT64)
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return static_cast<long double>(
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atan2(static_cast<double>(y), static_cast<double>(x)));
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math::atan2(static_cast<double>(y), static_cast<double>(x)));
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#else
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#error "Extended precision is not yet supported"
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#endif

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1807,7 +1807,7 @@ RISCVSingleStepBreakpointLocationsPredictor::GetBreakpointLocations(
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Log *log = GetLog(LLDBLog::Unwind);
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LLDB_LOGF(log,
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"RISCVSingleStepBreakpointLocationsPredictor::%s: can't find "
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"corresponding load reserve insturuction",
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"corresponding load reserve instruction",
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__FUNCTION__);
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return {*pc + (inst->is_rvc ? 2u : 4u)};
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}
@@ -1839,7 +1839,7 @@ RISCVSingleStepBreakpointLocationsPredictor::HandleAtomicSequence(
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EmulateInstructionRISCV *riscv_emulator =
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static_cast<EmulateInstructionRISCV *>(m_emulator_up.get());
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// Handle instructions between LR and SC. According to unprivilleged
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// Handle instructions between LR and SC. According to unprivileged
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// RISC-V ISA there can be at most 16 instructions in the sequence.
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lldb::addr_t entry_pc = pc; // LR instruction address
@@ -1872,7 +1872,7 @@ RISCVSingleStepBreakpointLocationsPredictor::HandleAtomicSequence(
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Log *log = GetLog(LLDBLog::Unwind);
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LLDB_LOGF(log,
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"RISCVSingleStepBreakpointLocationsPredictor::%s: can't find "
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"corresponding store conditional insturuction",
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"corresponding store conditional instruction",
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__FUNCTION__);
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return {entry_pc + (lr_inst->is_rvc ? 2u : 4u)};
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}

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