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| 1 | 1 | ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 | 
| 2 | 2 | ; RUN: opt -S -passes='dxil-data-scalarization' -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s | 
| 3 | 3 | 
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| 4 |  | -define float @extract_float_vec_dynamic(<4 x float> %0, i32 %1) { | 
|  | 4 | +define float @extract_float_vec_dynamic(<4 x float> %v, i32 %i) { | 
| 5 | 5 | ; CHECK-LABEL: define float @extract_float_vec_dynamic( | 
| 6 |  | -; CHECK-SAME: <4 x float> [[TMP0:%.*]], i32 [[TMP1:%.*]]) { | 
| 7 |  | -; CHECK-NEXT:    [[TMP3:%.*]] = alloca [4 x float], align 4 | 
| 8 |  | -; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP0]], i64 0 | 
| 9 |  | -; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP3]], i32 0, i32 0 | 
|  | 6 | +; CHECK-SAME: <4 x float> [[V:%.*]], i32 [[I:%.*]]) { | 
|  | 7 | +; CHECK-NEXT:    [[TMP1:%.*]] = alloca [4 x float], align 4 | 
|  | 8 | +; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[V]], i64 0 | 
|  | 9 | +; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP1]], i32 0, i32 0 | 
|  | 10 | +; CHECK-NEXT:    store float [[TMP2]], ptr [[TMP3]], align 4 | 
|  | 11 | +; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[V]], i64 1 | 
|  | 12 | +; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP1]], i32 0, i32 1 | 
| 10 | 13 | ; CHECK-NEXT:    store float [[TMP4]], ptr [[TMP5]], align 4 | 
| 11 |  | -; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP0]], i64 1 | 
| 12 |  | -; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP3]], i32 0, i32 1 | 
|  | 14 | +; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[V]], i64 2 | 
|  | 15 | +; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP1]], i32 0, i32 2 | 
| 13 | 16 | ; CHECK-NEXT:    store float [[TMP6]], ptr [[TMP7]], align 4 | 
| 14 |  | -; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <4 x float> [[TMP0]], i64 2 | 
| 15 |  | -; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP3]], i32 0, i32 2 | 
|  | 17 | +; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <4 x float> [[V]], i64 3 | 
|  | 18 | +; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP1]], i32 0, i32 3 | 
| 16 | 19 | ; CHECK-NEXT:    store float [[TMP8]], ptr [[TMP9]], align 4 | 
| 17 |  | -; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x float> [[TMP0]], i64 3 | 
| 18 |  | -; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP3]], i32 0, i32 3 | 
| 19 |  | -; CHECK-NEXT:    store float [[TMP10]], ptr [[TMP11]], align 4 | 
| 20 |  | -; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP3]], i32 0, i32 [[TMP1]] | 
| 21 |  | -; CHECK-NEXT:    [[TMP13:%.*]] = load float, ptr [[TMP12]], align 4 | 
| 22 |  | -; CHECK-NEXT:    ret float [[TMP13]] | 
|  | 20 | +; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP1]], i32 0, i32 [[I]] | 
|  | 21 | +; CHECK-NEXT:    [[TMP11:%.*]] = load float, ptr [[TMP10]], align 4 | 
|  | 22 | +; CHECK-NEXT:    ret float [[TMP11]] | 
| 23 | 23 | ; | 
| 24 |  | -  %e = extractelement <4 x float> %0, i32 %1 | 
| 25 |  | -  ret float %e | 
|  | 24 | +  %ee = extractelement <4 x float> %v, i32 %i | 
|  | 25 | +  ret float %ee | 
|  | 26 | +} | 
|  | 27 | + | 
|  | 28 | +define void @insert_i32_vec_dynamic(<3 x i32> %v, i32 %a, i32 %i) { | 
|  | 29 | +; CHECK-LABEL: define void @insert_i32_vec_dynamic( | 
|  | 30 | +; CHECK-SAME: <3 x i32> [[V:%.*]], i32 [[A:%.*]], i32 [[I:%.*]]) { | 
|  | 31 | +; CHECK-NEXT:    [[TMP1:%.*]] = alloca [3 x i32], align 4 | 
|  | 32 | +; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <3 x i32> [[V]], i64 0 | 
|  | 33 | +; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [3 x i32], ptr [[TMP1]], i32 0, i32 0 | 
|  | 34 | +; CHECK-NEXT:    store i32 [[TMP2]], ptr [[TMP3]], align 4 | 
|  | 35 | +; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <3 x i32> [[V]], i64 1 | 
|  | 36 | +; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i32], ptr [[TMP1]], i32 0, i32 1 | 
|  | 37 | +; CHECK-NEXT:    store i32 [[TMP4]], ptr [[TMP5]], align 4 | 
|  | 38 | +; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <3 x i32> [[V]], i64 2 | 
|  | 39 | +; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i32], ptr [[TMP1]], i32 0, i32 2 | 
|  | 40 | +; CHECK-NEXT:    store i32 [[TMP6]], ptr [[TMP7]], align 4 | 
|  | 41 | +; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x i32], ptr [[TMP1]], i32 0, i32 [[I]] | 
|  | 42 | +; CHECK-NEXT:    store i32 [[A]], ptr [[TMP8]], align 4 | 
|  | 43 | +; CHECK-NEXT:    ret void | 
|  | 44 | +; | 
|  | 45 | +  insertelement <3 x i32> %v, i32 %a, i32 %i | 
|  | 46 | +  ret void | 
| 26 | 47 | } | 
| 27 | 48 | 
 | 
| 28 | 49 | ; An extractelement with a constant index should not be converted to array form | 
| 29 |  | -define i16 @extract_i16_vec_constant(<4 x i16> %0) { | 
|  | 50 | +define i16 @extract_i16_vec_constant(<4 x i16> %v) { | 
| 30 | 51 | ; CHECK-LABEL: define i16 @extract_i16_vec_constant( | 
| 31 |  | -; CHECK-SAME: <4 x i16> [[TMP0:%.*]]) { | 
| 32 |  | -; CHECK-NEXT:    [[E:%.*]] = extractelement <4 x i16> [[TMP0]], i32 1 | 
| 33 |  | -; CHECK-NEXT:    ret i16 [[E]] | 
|  | 52 | +; CHECK-SAME: <4 x i16> [[V:%.*]]) { | 
|  | 53 | +; CHECK-NEXT:    [[EE:%.*]] = extractelement <4 x i16> [[V]], i32 1 | 
|  | 54 | +; CHECK-NEXT:    ret i16 [[EE]] | 
|  | 55 | +; | 
|  | 56 | +  %ee = extractelement <4 x i16> %v, i32 1 | 
|  | 57 | +  ret i16 %ee | 
|  | 58 | +} | 
|  | 59 | + | 
|  | 60 | +; An insertelement with a constant index should not be converted to array form | 
|  | 61 | +define void @insert_half_vec_constant(<2 x half> %v, half %a) { | 
|  | 62 | +; CHECK-LABEL: define void @insert_half_vec_constant( | 
|  | 63 | +; CHECK-SAME: <2 x half> [[V:%.*]], half [[A:%.*]]) { | 
|  | 64 | +; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x half> [[V]], half [[A]], i32 1 | 
|  | 65 | +; CHECK-NEXT:    ret void | 
| 34 | 66 | ; | 
| 35 |  | -  %e = extractelement <4 x i16> %0, i32 1 | 
| 36 |  | -  ret i16 %e | 
|  | 67 | +  insertelement <2 x half> %v, half %a, i32 1 | 
|  | 68 | +  ret void | 
| 37 | 69 | } | 
| 38 | 70 | 
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