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[RISCV] Remove duplicate vector conversion pseudos.
These pseudos used to be handled by CustomInserter to insert the rounding mode change for vector ceil, floor, etc. At some point they were changed to use the InsertReadWriteCSR pass instead of the custom inserter. I believe that makes them redundant with the pseudos used by the RVV intrinsics with rounding mode operand.
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2 files changed

+10
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 0 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -1130,46 +1130,6 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
11301130
let usesCustomInserter = 1;
11311131
}
11321132

1133-
class VPseudoUnaryNoMask_FRM<VReg RetClass,
1134-
VReg OpClass,
1135-
string Constraint = "",
1136-
bits<2> TargetConstraintType = 1> :
1137-
Pseudo<(outs RetClass:$rd),
1138-
(ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm,
1139-
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1140-
RISCVVPseudo {
1141-
let mayLoad = 0;
1142-
let mayStore = 0;
1143-
let hasSideEffects = 0;
1144-
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
1145-
let TargetOverlapConstraintType = TargetConstraintType;
1146-
let HasVLOp = 1;
1147-
let HasSEWOp = 1;
1148-
let HasVecPolicyOp = 1;
1149-
let HasRoundModeOp = 1;
1150-
}
1151-
1152-
class VPseudoUnaryMask_FRM<VReg RetClass,
1153-
VReg OpClass,
1154-
string Constraint = "",
1155-
bits<2> TargetConstraintType = 1> :
1156-
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
1157-
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1158-
VMaskOp:$vm, ixlenimm:$frm,
1159-
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1160-
RISCVVPseudo {
1161-
let mayLoad = 0;
1162-
let mayStore = 0;
1163-
let hasSideEffects = 0;
1164-
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
1165-
let TargetOverlapConstraintType = TargetConstraintType;
1166-
let HasVLOp = 1;
1167-
let HasSEWOp = 1;
1168-
let HasVecPolicyOp = 1;
1169-
let UsesMaskPolicy = 1;
1170-
let HasRoundModeOp = 1;
1171-
}
1172-
11731133
class VPseudoUnaryNoMaskGPROut :
11741134
Pseudo<(outs GPR:$rd),
11751135
(ins VR:$rs2, AVL:$vl, sew:$sew), []>,
@@ -3574,23 +3534,6 @@ multiclass VPseudoConversionRoundingMode<VReg RetClass,
35743534
}
35753535
}
35763536

3577-
3578-
multiclass VPseudoConversionRM<VReg RetClass,
3579-
VReg Op1Class,
3580-
LMULInfo MInfo,
3581-
string Constraint = "",
3582-
int sew = 0,
3583-
bits<2> TargetConstraintType = 1> {
3584-
let VLMul = MInfo.value, SEW=sew in {
3585-
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3586-
def suffix : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
3587-
Constraint, TargetConstraintType>;
3588-
def suffix # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
3589-
Constraint, TargetConstraintType>,
3590-
RISCVMaskedPseudo<MaskIdx=2>;
3591-
}
3592-
}
3593-
35943537
multiclass VPseudoConversionNoExcept<VReg RetClass,
35953538
VReg Op1Class,
35963539
LMULInfo MInfo,
@@ -3616,14 +3559,6 @@ multiclass VPseudoVCVTI_V_RM {
36163559
}
36173560
}
36183561

3619-
multiclass VPseudoVCVTI_RM_V {
3620-
foreach m = MxListF in {
3621-
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
3622-
SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,
3623-
forcePassthruRead=true>;
3624-
}
3625-
}
3626-
36273562
multiclass VPseudoVFROUND_NOEXCEPT_V {
36283563
foreach m = MxListF in {
36293564
defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m>,
@@ -3641,15 +3576,6 @@ multiclass VPseudoVCVTF_V_RM {
36413576
}
36423577
}
36433578

3644-
multiclass VPseudoVCVTF_RM_V {
3645-
foreach m = MxListF in {
3646-
foreach e = SchedSEWSet<m.MX, isF=1>.val in
3647-
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m, sew=e>,
3648-
SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,
3649-
forcePassthruRead=true>;
3650-
}
3651-
}
3652-
36533579
multiclass VPseudoVWCVTI_V {
36543580
defvar constraint = "@earlyclobber $rd";
36553581
foreach m = MxListFW in {
@@ -3668,15 +3594,6 @@ multiclass VPseudoVWCVTI_V_RM {
36683594
}
36693595
}
36703596

3671-
multiclass VPseudoVWCVTI_RM_V {
3672-
defvar constraint = "@earlyclobber $rd";
3673-
foreach m = MxListFW in {
3674-
defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
3675-
SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
3676-
forcePassthruRead=true>;
3677-
}
3678-
}
3679-
36803597
multiclass VPseudoVWCVTF_V {
36813598
defvar constraint = "@earlyclobber $rd";
36823599
foreach m = MxListW in {
@@ -3717,15 +3634,6 @@ multiclass VPseudoVNCVTI_W_RM {
37173634
}
37183635
}
37193636

3720-
multiclass VPseudoVNCVTI_RM_W {
3721-
defvar constraint = "@earlyclobber $rd";
3722-
foreach m = MxListW in {
3723-
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
3724-
SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
3725-
forcePassthruRead=true>;
3726-
}
3727-
}
3728-
37293637
multiclass VPseudoVNCVTF_W_RM {
37303638
defvar constraint = "@earlyclobber $rd";
37313639
foreach m = MxListFW in {
@@ -3738,17 +3646,6 @@ multiclass VPseudoVNCVTF_W_RM {
37383646
}
37393647
}
37403648

3741-
multiclass VPseudoVNCVTF_RM_W {
3742-
defvar constraint = "@earlyclobber $rd";
3743-
foreach m = MxListFW in {
3744-
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3745-
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, sew=e,
3746-
TargetConstraintType=2>,
3747-
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
3748-
forcePassthruRead=true>;
3749-
}
3750-
}
3751-
37523649
multiclass VPseudoVNCVTD_W {
37533650
defvar constraint = "@earlyclobber $rd";
37543651
foreach m = MxListFW in {
@@ -6579,9 +6476,6 @@ defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM;
65796476
defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM;
65806477
}
65816478

6582-
defm PseudoVFCVT_RM_XU_F : VPseudoVCVTI_RM_V;
6583-
defm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V;
6584-
65856479
defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
65866480
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
65876481

@@ -6590,8 +6484,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
65906484
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM;
65916485
defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM;
65926486
}
6593-
defm PseudoVFCVT_RM_F_XU : VPseudoVCVTF_RM_V;
6594-
defm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V;
65956487
} // mayRaiseFPException = true
65966488

65976489
//===----------------------------------------------------------------------===//
@@ -6602,8 +6494,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
66026494
defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM;
66036495
defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM;
66046496
}
6605-
defm PseudoVFWCVT_RM_XU_F : VPseudoVWCVTI_RM_V;
6606-
defm PseudoVFWCVT_RM_X_F : VPseudoVWCVTI_RM_V;
66076497

66086498
defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
66096499
defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V;
@@ -6623,8 +6513,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
66236513
defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM;
66246514
defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM;
66256515
}
6626-
defm PseudoVFNCVT_RM_XU_F : VPseudoVNCVTI_RM_W;
6627-
defm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W;
66286516

66296517
defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
66306518
defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;
@@ -6633,8 +6521,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
66336521
defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM;
66346522
defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
66356523
}
6636-
defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W;
6637-
defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W;
66386524

66396525
let hasSideEffects = 0, hasPostISelHook = 1 in {
66406526
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2639,23 +2639,23 @@ foreach fvti = AllFloatVectors in {
26392639
// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
26402640
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">;
26412641
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">;
2642-
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_RM_XU_F_V">;
2643-
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_RM_X_F_V">;
2642+
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_XU_F_V">;
2643+
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_X_F_V">;
26442644

26452645
defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFCVT_RTZ_XU_F_V">;
26462646
defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFCVT_RTZ_X_F_V">;
26472647

26482648
defm : VPatConvertI2FPVL_V_RM<any_riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
26492649
defm : VPatConvertI2FPVL_V_RM<any_riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;
26502650

2651-
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_RM_F_XU_V">;
2652-
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_RM_F_X_V">;
2651+
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_F_XU_V">;
2652+
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_F_X_V">;
26532653

26542654
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
26552655
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
26562656
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFWCVT_X_F_V">;
2657-
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_RM_XU_F_V">;
2658-
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_RM_X_F_V">;
2657+
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
2658+
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_X_F_V">;
26592659

26602660
defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
26612661
defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">;
@@ -2696,17 +2696,17 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
26962696
// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
26972697
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
26982698
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_x_f_vl, "PseudoVFNCVT_X_F_W">;
2699-
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_RM_XU_F_W">;
2700-
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_RM_X_F_W">;
2699+
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
2700+
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;
27012701

27022702
defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
27032703
defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F_W">;
27042704

27052705
defm : VPatNConvertI2FPVL_W_RM<any_riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;
27062706
defm : VPatNConvertI2FPVL_W_RM<any_riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;
27072707

2708-
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_RM_F_XU_W">;
2709-
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_RM_F_X_W">;
2708+
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_F_XU_W">;
2709+
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_F_X_W">;
27102710

27112711
foreach fvtiToFWti = AllWidenableFloatVectors in {
27122712
defvar fvti = fvtiToFWti.Vti;

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