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[Xtensa] Implement Xtensa Region Protection Option and several other small Options. (#137135)
Implement support of the Xtensa Region Protection, Extended L32R, Data Cache, Relocatable Vector and MISC Special Registers Options.
1 parent d771e4d commit 160d9d5

30 files changed

+950
-15
lines changed

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 18 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -105,28 +105,37 @@ static const MCPhysReg MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3};
105105
static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
106106
uint64_t Address,
107107
const void *Decoder) {
108-
if (RegNo != 2 && RegNo != 3)
108+
if (RegNo != 0 && RegNo != 1)
109109
return MCDisassembler::Fail;
110110

111-
MCPhysReg Reg = MR23DecoderTable[RegNo - 2];
111+
MCPhysReg Reg = MR23DecoderTable[RegNo];
112112
Inst.addOperand(MCOperand::createReg(Reg));
113113
return MCDisassembler::Success;
114114
}
115115

116-
const MCPhysReg SRDecoderTable[] = {
117-
Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
118-
Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
119-
Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
116+
struct DecodeRegister {
117+
MCPhysReg Reg;
118+
uint32_t RegNo;
119+
};
120+
121+
const DecodeRegister SRDecoderTable[] = {
122+
{Xtensa::LBEG, 0}, {Xtensa::LEND, 1}, {Xtensa::LCOUNT, 2},
123+
{Xtensa::SAR, 3}, {Xtensa::BREG, 4}, {Xtensa::SAR, 3},
124+
{Xtensa::LITBASE, 5}, {Xtensa::ACCLO, 16}, {Xtensa::ACCHI, 17},
125+
{Xtensa::M0, 32}, {Xtensa::M1, 33}, {Xtensa::M2, 34},
126+
{Xtensa::M3, 35}, {Xtensa::WINDOWBASE, 72}, {Xtensa::WINDOWSTART, 73},
127+
{Xtensa::MEMCTL, 97}, {Xtensa::VECBASE, 231}, {Xtensa::MISC0, 244},
128+
{Xtensa::MISC1, 245}, {Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};
120129

121130
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
122131
uint64_t Address,
123132
const MCDisassembler *Decoder) {
124133
if (RegNo > 255)
125134
return MCDisassembler::Fail;
126135

127-
for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
128-
if (SRDecoderTable[i + 1] == RegNo) {
129-
MCPhysReg Reg = SRDecoderTable[i];
136+
for (unsigned i = 0; i < std::size(SRDecoderTable); i++) {
137+
if (SRDecoderTable[i].RegNo == RegNo) {
138+
MCPhysReg Reg = SRDecoderTable[i].Reg;
130139

131140
if (!Xtensa::checkRegister(Reg,
132141
Decoder->getSubtargetInfo().getFeatureBits()))

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,24 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
8383
case Xtensa::LEND:
8484
case Xtensa::LCOUNT:
8585
return FeatureBits[Xtensa::FeatureLoop];
86+
case Xtensa::LITBASE:
87+
return FeatureBits[Xtensa::FeatureExtendedL32R];
88+
case Xtensa::MEMCTL:
89+
return FeatureBits[Xtensa::FeatureDataCache];
90+
case Xtensa::ACCLO:
91+
case Xtensa::ACCHI:
92+
case Xtensa::M0:
93+
case Xtensa::M1:
94+
case Xtensa::M2:
95+
case Xtensa::M3:
96+
return FeatureBits[Xtensa::FeatureMAC16];
97+
case Xtensa::MISC0:
98+
case Xtensa::MISC1:
99+
case Xtensa::MISC2:
100+
case Xtensa::MISC3:
101+
return FeatureBits[Xtensa::FeatureMiscSR];
102+
case Xtensa::VECBASE:
103+
return FeatureBits[Xtensa::FeatureRelocatableVector];
86104
case Xtensa::WINDOWBASE:
87105
case Xtensa::WINDOWSTART:
88106
return FeatureBits[Xtensa::FeatureWindowed];

‎llvm/lib/Target/Xtensa/XtensaFeatures.td‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,3 +67,28 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
6767
"Enable Xtensa Div32 option">;
6868
def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
6969
AssemblerPredicate<(all_of FeatureDiv32)>;
70+
71+
def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true",
72+
"Enable Xtensa Region Protection option">;
73+
def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">,
74+
AssemblerPredicate<(all_of FeatureRegionProtection)>;
75+
76+
def FeatureRelocatableVector : SubtargetFeature<"rvector", "HasRelocatableVector", "true",
77+
"Enable Xtensa Relocatable Vector option">;
78+
def HasRelocatableVector : Predicate<"Subtarget->hasRelocatableVector()">,
79+
AssemblerPredicate<(all_of FeatureRelocatableVector)>;
80+
81+
def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true",
82+
"Enable Xtensa Miscellaneous SR option">;
83+
def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">,
84+
AssemblerPredicate<(all_of FeatureMiscSR)>;
85+
86+
def FeatureExtendedL32R : SubtargetFeature<"extendedl32r", "HasExtendedL32R", "true",
87+
"Enable Xtensa Extended L32R option">;
88+
def HasExtendedL32R : Predicate<"Subtarget->hasExtendedL32R()">,
89+
AssemblerPredicate<(all_of FeatureExtendedL32R)>;
90+
91+
def FeatureDataCache : SubtargetFeature<"dcache", "HasDataCache", "true",
92+
"Enable Xtensa Data Cache option">;
93+
def HasDataCache : Predicate<"Subtarget->hasDataCache()">,
94+
AssemblerPredicate<(all_of FeatureDataCache)>;

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -986,6 +986,64 @@ let Predicates = [HasDiv32] in {
986986
def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
987987
}
988988

989+
//===----------------------------------------------------------------------===//
990+
// Region Protection feature instructions
991+
//===----------------------------------------------------------------------===//
992+
993+
let Predicates = [HasRegionProtection] in {
994+
def IDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
995+
"idtlb\t$s", []> {
996+
let r = 0xC;
997+
let t = 0x0;
998+
}
999+
1000+
def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
1001+
"iitlb\t$s", []> {
1002+
let r = 0x4;
1003+
let t = 0x0;
1004+
}
1005+
1006+
def PDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1007+
"pdtlb\t$t, $s", []> {
1008+
let r = 0xD;
1009+
}
1010+
1011+
def PITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1012+
"pitlb\t$t, $s", []> {
1013+
let r = 0x5;
1014+
}
1015+
1016+
def RDTLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1017+
"rdtlb0\t$t, $s", []> {
1018+
let r = 0xB;
1019+
}
1020+
1021+
def RDTLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1022+
"rdtlb1\t$t, $s", []> {
1023+
let r = 0xF;
1024+
}
1025+
1026+
def RITLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1027+
"ritlb0\t$t, $s", []> {
1028+
let r = 0x3;
1029+
}
1030+
1031+
def RITLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1032+
"ritlb1\t$t, $s", []> {
1033+
let r = 0x7;
1034+
}
1035+
1036+
def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1037+
"wdtlb\t$t, $s", []> {
1038+
let r = 0xE;
1039+
}
1040+
1041+
def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1042+
"witlb\t$t, $s", []> {
1043+
let r = 0x6;
1044+
}
1045+
}
1046+
9891047
//===----------------------------------------------------------------------===//
9901048
// DSP Instructions
9911049
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Xtensa/XtensaRegisterInfo.td‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,10 +84,25 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>;
8484
// Boolean Register
8585
def BREG : SRReg<4, "br", ["BR","4"]>;
8686

87+
// Literal base
88+
def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>;
89+
8790
// Windowed Register Option registers
8891
def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;
8992
def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;
9093

94+
// Memory Control Register
95+
def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;
96+
97+
// Vector base register
98+
def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;
99+
100+
// Xtensa Miscellaneous SR
101+
def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;
102+
def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;
103+
def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;
104+
def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;
105+
91106
// MAC16 Option registers
92107
def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;
93108
def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;
@@ -101,7 +116,8 @@ def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
101116
def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
102117

103118
def SR : RegisterClass<"Xtensa", [i32], 32, (add
104-
LBEG, LEND, LCOUNT, SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>;
119+
LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART,
120+
MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
105121

106122
//===----------------------------------------------------------------------===//
107123
// Boolean registers

‎llvm/lib/Target/Xtensa/XtensaSubtarget.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,11 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
7777
bool hasMul32() const { return HasMul32; }
7878
bool hasMul32High() const { return HasMul32High; }
7979
bool hasDiv32() const { return HasDiv32; }
80+
bool hasRegionProtection() const { return HasRegionProtection; }
81+
bool hasRelocatableVector() const { return HasRelocatableVector; }
82+
bool hasMiscSR() const { return HasMiscSR; }
83+
bool hasExtendedL32R() const { return HasExtendedL32R; }
84+
bool hasDataCache() const { return HasDataCache; }
8085
bool isWindowedABI() const { return hasWindowed(); }
8186

8287
// Automatically generated by tblgen.

‎llvm/test/MC/Disassembler/Xtensa/clamps.txt‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+clamps -disassemble %s | FileCheck -check-prefixes=CHECK-CLAMPS %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## clamps option enabled. Also verify that dissasembling without
6+
## clamps option generates warnings.
7+
8+
[0x00,0x34,0x33]
9+
# CHECK-CLAMPS: clamps a3, a4, 7
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Disassembler/Xtensa/code_density.txt‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,9 @@
11
# RUN: llvm-mc -triple=xtensa -mattr=+density -disassemble %s | FileCheck -check-prefixes=CHECK-DENSITY %s
22
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
33

4-
#------------------------------------------------------------------------------
5-
# Verify that binary code is correctly disassembled with
6-
# code density option enabled. Also verify that dissasembling without
7-
# density option generates warnings.
8-
#------------------------------------------------------------------------------
4+
## Verify that binary code is correctly disassembled with
5+
## code density option enabled. Also verify that dissasembling without
6+
## density option generates warnings.
97

108
[0x4a, 0x23]
119
# CHECK-DENSITY: add.n a2, a3, a4

‎llvm/test/MC/Disassembler/Xtensa/dcache.txt‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+dcache -disassemble %s | FileCheck -check-prefixes=CHECK-DCACHE %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## dcache option enabled. Also verify that dissasembling without
6+
## dcache option generates warnings.
7+
8+
[0x30,0x61,0x61]
9+
# CHECK-DCACHE: xsr a3, memctl
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Disassembler/Xtensa/div.txt‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+div32 -disassemble %s | FileCheck -check-prefixes=CHECK-DIV32 %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## div32 option enabled. Also verify that dissasembling without
6+
## div32 option generates warnings.
7+
8+
[0x50,0x34,0xd2]
9+
# CHECK-DIV32: quos a3, a4, a5
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
11+
12+
[0x50,0x34,0xc2]
13+
# CHECK-DIV32: quou a3, a4, a5
14+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
15+
16+
[0x50,0x34,0xf2]
17+
# CHECK-DIV32: rems a3, a4, a5
18+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
19+
20+
[0x50,0x34,0xe2]
21+
# CHECK-DIV32: remu a3, a4, a5
22+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

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