Review changes:

 - Add tests
 - Remove builtin (users will need inline assembly if pattern match fails)

Author: linuxrocks123

clang/include/clang/Basic/BuiltinsAMDGPU.def

@@ -63,9 +63,6 @@ BUILTIN(__builtin_amdgcn_grid_size_z, "Ui", "nc")
 BUILTIN(__builtin_amdgcn_mbcnt_hi, "UiUiUi", "nc")
 BUILTIN(__builtin_amdgcn_mbcnt_lo, "UiUiUi", "nc")
 
-BUILTIN(__builtin_amdgcn_bcnt32_lo, "UiUi", "nc")
-BUILTIN(__builtin_amdgcn_bcnt64_lo, "UiWUi", "nc")
-
 TARGET_BUILTIN(__builtin_amdgcn_s_memtime, "WUi", "n", "s-memtime-inst")
 
 //===----------------------------------------------------------------------===//

llvm/include/llvm/IR/IntrinsicsAMDGPU.td

@@ -2360,11 +2360,9 @@ def int_amdgcn_mbcnt_hi :
             [IntrNoMem]>;
 
 def int_amdgcn_bcnt32_lo :
-  ClangBuiltin<"__builtin_amdgcn_bcnt32_lo">,
   DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 
 def int_amdgcn_bcnt64_lo :
-  ClangBuiltin<"__builtin_amdgcn_bcnt64_lo">,
   DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>;
 
 // llvm.amdgcn.ds.swizzle src offset

llvm/test/CodeGen/AMDGPU/s_cmp_0.ll

@@ -621,3 +621,112 @@ if:
 endif:
   ret i32 1
 }
+
+define amdgpu_ps void @bcnt032_not_for_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; CHECK-LABEL: bcnt032_not_for_vregs:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_lshl_b32 s0, s0, 2
+; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
+; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT: global_load_dword v2, v[2:3], off glc
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; CHECK-NEXT: v_sub_u32_e32 v3, 32, v2
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use v3
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: global_store_dword v[0:1], v2, off
+; CHECK-NEXT: s_endpgm
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
+  %val0 = load volatile i32, ptr addrspace(1) %gep
+  %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
+  %result2 = sub i32 32, %result
+  call void asm "; use $0", "s"(i32 %result2)
+  %cmp = icmp ne i32 %result2, 0
+  %zext = zext i1 %cmp to i32
+  store i32 %result, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_ps void @bcnt064_not_for_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; CHECK-LABEL: bcnt064_not_for_vregs:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: b32 s0, s0, 2
+; CHECK-NEXT: o_u32_e32 v2, vcc, s0, v2
+; CHECK-NEXT: co_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT: load_dwordx2 v[2:3], v[2:3], off glc
+; CHECK-NEXT: nt vmcnt(0)
+; CHECK-NEXT: 32_e32 v4, 0
+; CHECK-NEXT: u32_b32 v2, v2, 0
+; CHECK-NEXT: u32_b32 v3, v3, v2
+; CHECK-NEXT: o_u32_e32 v5, vcc, 64, v3
+; CHECK-NEXT: co_u32_e64 v6, s[0:1], 0, 0, vcc
+; CHECK-NEXT: TART
+; CHECK-NEXT: [5:6]
+; CHECK-NEXT: ND
+; CHECK-NEXT: store_dwordx2 v[0:1], v[3:4], off
+; CHECK-NEXT: m
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
+  %val0 = load volatile i64, ptr addrspace(1) %gep
+  %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone
+  %result2 = sub i64 64, %result
+  call void asm "; use $0", "s"(i64 %result2)
+  %cmp = icmp ne i64 %result2, 0
+  %zext = zext i1 %cmp to i32
+  store i64 %result, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_ps i32 @bcnt032_ctpop_multiple_uses(i32 inreg %val0) {
+; CHECK-LABEL: bcnt032_ctpop_multiple_uses:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT: _i32_b32 s0, s0
+; CHECK-NEXT: 32 s1, 32, s0
+; CHECK-NEXT: g_u32 s1, 0
+; CHECK-NEXT: TART
+; CHECK-NEXT: 0
+; CHECK-NEXT: ND
+; CHECK-NEXT: TART
+; CHECK-NEXT: 1
+; CHECK-NEXT: ND
+; CHECK-NEXT: ct_b64 s[0:1], -1, 0
+; CHECK-NEXT: sk_b32_e64 v0, 0, 1, s[0:1]
+; CHECK-NEXT: irstlane_b32 s0, v0
+; CHECK-NEXT: n to shader part epilog
+  %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
+  %result2 = sub i32 32, %result
+  call void asm "; use $0", "s"(i32 %result)
+  call void asm "; use $0", "s"(i32 %result2)
+  %cmp = icmp ne i32 %result2, 0
+  %zext = zext i1 %cmp to i32
+  ret i32 %zext
+}
+
+define amdgpu_ps i32 @bcnt064_ctpop_multiple_uses(i64 inreg %val0) {
+; CHECK-LABEL: bcnt064_ctpop_multiple_uses:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT: _i32_b64 s0, s[0:1]
+; CHECK-NEXT: 32 s2, 64, s0
+; CHECK-NEXT: u32 s3, 0, 0
+; CHECK-NEXT: 32 s1, 0
+; CHECK-NEXT: g_u64 s[2:3], 0
+; CHECK-NEXT: TART
+; CHECK-NEXT: [0:1]
+; CHECK-NEXT: ND
+; CHECK-NEXT: ct_b64 s[0:1], -1, 0
+; CHECK-NEXT: sk_b32_e64 v0, 0, 1, s[0:1]
+; CHECK-NEXT: irstlane_b32 s0, v0
+; CHECK-NEXT: TART
+; CHECK-NEXT: [2:3]
+; CHECK-NEXT: ND
+; CHECK-NEXT: n to shader part epilog
+  %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone
+  %result2 = sub i64 64, %result
+  call void asm "; use $0", "s"(i64 %result)
+  call void asm "; use $0", "s"(i64 %result2)
+  %cmp = icmp ne i64 %result2, 0
+  %zext = zext i1 %cmp to i32
+  ret i32 %zext
+}