fixup! Split out the folding rule on interleave2 of two const splats

Author: mshockwave

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -22665,47 +22665,6 @@ bool RISCVTargetLowering::lowerDeinterleavedIntrinsicToVPLoad(
   return true;
 }
 
-/// If we're interleaving 2 constant splats, for instance `<vscale x 8 x i32>
-/// <splat of 666>` and `<vscale x 8 x i32> <splat of 777>`, we can create a
-/// larger splat
-/// `<vscale x 4 x i64> <splat of ((777 << 32) | 666)>` first before casting it
-/// into
-/// `<vscale x 8 x i32>`. This will resuling a simple unit stride store rather
-/// than a segment store, which is more expensive in this case.
-static Value *foldInterleaved2OfConstSplats(Value *Op0, Value *Op1,
-                                            VectorType *VTy,
-                                            const TargetLowering *TLI,
-                                            Instruction *VPStore) {
-  auto *SplatVal0 = dyn_cast_or_null<ConstantInt>(getSplatValue(Op0));
-  auto *SplatVal1 = dyn_cast_or_null<ConstantInt>(getSplatValue(Op1));
-  if (!SplatVal0 || !SplatVal1)
-    return nullptr;
-
-  auto &Ctx = VPStore->getContext();
-  auto &DL = VPStore->getModule()->getDataLayout();
-
-  auto *NewVTy = VectorType::getExtendedElementVectorType(VTy);
-  if (!TLI->isTypeLegal(TLI->getValueType(DL, NewVTy)))
-    return nullptr;
-
-  // InterleavedAccessPass will remove VPStore after this but we still want to
-  // preserve it, hence clone another one here.
-  auto *ClonedVPStore = VPStore->clone();
-  ClonedVPStore->insertBefore(VPStore);
-  IRBuilder<> Builder(ClonedVPStore);
-
-  Type *ETy = VTy->getElementType();
-  unsigned Width = ETy->getIntegerBitWidth();
-
-  APInt NewSplatVal(Width * 2, SplatVal1->getZExtValue());
-  NewSplatVal <<= Width;
-  NewSplatVal |= SplatVal0->getZExtValue();
-  auto *NewSplat = ConstantVector::getSplat(NewVTy->getElementCount(),
-                                            ConstantInt::get(Ctx, NewSplatVal));
-  return Builder.CreateBitCast(NewSplat,
-                               VectorType::getDoubleElementsVectorType(VTy));
-}
-
 /// Lower an interleaved vp.store into a vssegN intrinsic.
 ///
 /// E.g. Lower an interleaved vp.store (Factor = 2):
@@ -22748,14 +22707,6 @@ bool RISCVTargetLowering::lowerInterleavedIntrinsicToVPStore(
           Store->getArgOperand(1)->getType()->getPointerAddressSpace(), DL))
     return false;
 
-  if (Factor == 2)
-    if (Value *BC = foldInterleaved2OfConstSplats(
-            InterleaveOperands[0], InterleaveOperands[1], VTy, this, Store)) {
-      // Store is guranteed to be the only user of the interleaved intrinsic.
-      Store->getOperand(0)->replaceAllUsesWith(BC);
-      return true;
-    }
-
   IRBuilder<> Builder(Store);
   Value *WideEVL = Store->getArgOperand(3);
   // Conservatively check if EVL is a multiple of factor, otherwise some

llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll

@@ -137,42 +137,6 @@ define void @store_factor2_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, pt
   ret void
 }
 
-; Expecting unit-stride store here rather than segmented store.
-define void @store_factor2_const_splat(ptr %dst) {
-; RV32-LABEL: store_factor2_const_splat:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    li a1, 777
-; RV32-NEXT:    li a2, 666
-; RV32-NEXT:    sw a2, 8(sp)
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    addi a1, sp, 8
-; RV32-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
-; RV32-NEXT:    vlse64.v v8, (a1), zero
-; RV32-NEXT:    li a1, 88
-; RV32-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    .cfi_def_cfa_offset 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: store_factor2_const_splat:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a1, 777
-; RV64-NEXT:    slli a1, a1, 32
-; RV64-NEXT:    addi a1, a1, 666
-; RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
-; RV64-NEXT:    vmv.v.x v8, a1
-; RV64-NEXT:    li a1, 88
-; RV64-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
-  %interleave2 = call <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32> splat (i32 666), <vscale x 8 x i32> splat (i32 777))
-  call void @llvm.vp.store.nxv16i32.p0(<vscale x 16 x i32> %interleave2, ptr %dst, <vscale x 16 x i1> splat (i1 true), i32 88)
-  ret void
-}
-
 define void @store_factor4_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, ptr %ptr, i32 %evl) {
 ; RV32-LABEL: store_factor4_v2:
 ; RV32:       # %bb.0: