Another fix (dead destination reg)

Author: sdesmalen-arm

llvm/lib/CodeGen/RegisterCoalescer.cpp

@@ -1930,6 +1930,7 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
       Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
 
     bool FullDef = true;
+    bool DeadDef = false;
 
     // Replace SrcReg with DstReg in all UseMI operands.
     for (unsigned Op : Ops) {
@@ -1941,6 +1942,7 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
       if (SubIdx && MO.isDef()) {
         MO.setIsUndef(!Reads);
         FullDef = false;
+        DeadDef = MO.isDead();
       }
 
       // A subreg use of a partially undef (super) register may be a complete
@@ -1974,7 +1976,7 @@ void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
         MO.substVirtReg(DstReg, SubIdx, *TRI);
     }
 
-    if (IsSubregToReg && !FullDef) {
+    if (IsSubregToReg && !FullDef && !DeadDef) {
       // If the coalesed instruction doesn't fully define the register, we need
       // to preserve the original super register liveness for SUBREG_TO_REG.
       //

llvm/test/CodeGen/X86/coalescer-subreg-to-reg-implicit-def-regression.mir

@@ -27,7 +27,7 @@ body: |
   ; CHECK-NEXT:   MOVAPSmr $noreg, 1, $noreg, 16, $noreg, [[V_SET0_]]
   ; CHECK-NEXT:   MOVAPSmr $noreg, 1, $noreg, 0, $noreg, [[V_SET0_]]
   ; CHECK-NEXT:   dead [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
-  ; CHECK-NEXT:   dead [[DEF:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = OR32ri [[DEF]].sub_32bit, 1, implicit-def $eflags, implicit-def [[DEF]]
+  ; CHECK-NEXT:   dead [[DEF:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = OR32ri [[DEF]].sub_32bit, 1, implicit-def $eflags
   ; CHECK-NEXT:   JMP_1 %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3: